Commit d3a21f7e authored by Felix Kuehling's avatar Felix Kuehling Committed by Alex Deucher
Browse files

drm/amdgpu: Fix MMIO HDP flush on SRIOV 



Disable HDP register remapping on SRIOV and set rmmio_remap.reg_offset
to the fixed address of the VF register for hdp_v*_flush_hdp.

Signed-off-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Tested-by: default avatarBokun Zhang <bokun.zhang@amd.com>
Reviewed-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 13605725

drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c

+4 −0
Original line number Diff line number Diff line
@@ -359,6 +359,10 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev) 


	if (def != data)

		WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);



	if (amdgpu_sriov_vf(adev))

		adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

			mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;

}



#define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT		0x00000000 // off by default, no gains over L1

drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c

+4 −0
Original line number Diff line number Diff line
@@ -276,6 +276,10 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev) 


	if (def != data)

		WREG32_PCIE(smnPCIE_CI_CNTL, data);



	if (amdgpu_sriov_vf(adev))

		adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

			mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;

}



static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c

+3 −1
Original line number Diff line number Diff line
@@ -273,7 +273,9 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = { 


static void nbio_v7_0_init_registers(struct amdgpu_device *adev)

{



	if (amdgpu_sriov_vf(adev))

		adev->rmmio_remap.reg_offset =

			SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;

}



const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {

drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c

+4 −0
Original line number Diff line number Diff line
@@ -371,6 +371,10 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev) 
		if (def != data)

			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);

	}



	if (amdgpu_sriov_vf(adev))

		adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

			regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;

}



const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+3 −1
Original line number Diff line number Diff line
@@ -362,7 +362,9 @@ const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg_ald = { 


static void nbio_v7_4_init_registers(struct amdgpu_device *adev)

{



	if (amdgpu_sriov_vf(adev))

		adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,

			mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;

}



static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)