Commit d39afb73 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v5.20-tag1' of... 

Merge tag 'renesas-clk-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add GPT/POEG (PWM) clocks and resets on RZ/G2L
 - Add PFC and WDT clocks and resets on RZ/V2M
 - Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
   R-Car S4-8
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v5.20-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779f0: Add HSCIF clocks
  clk: renesas: r8a779f0: Add PCIe clocks
  clk: renesas: r8a779f0: Add Z0 and Z1 clock support
  dt-bindings: clock: renesas,rzg2l: Simplify header file references
  clk: renesas: rza1: Remove struct rz_cpg
  clk: renesas: r8a7779: Remove struct r8a7779_cpg
  clk: renesas: r8a7778: Remove struct r8a7778_cpg
  clk: renesas: sh73a0: Remove sh73a0_cpg.reg
  clk: renesas: r8a7740: Remove r8a7740_cpg.reg
  clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg
  clk: renesas: r8a779f0: Add SDHI0 clock
  clk: renesas: r8a779f0: Add thermal clock
  clk: renesas: rzg2l: Fix reset status function
  clk: renesas: r9a06g032: Fix UART clkgrp bitsel
  clk: renesas: r9a06g032: Drop some unused fields
  clk: renesas: r9a09g011: Add WDT clock and reset entries
  clk: renesas: r9a09g011: Add PFC clock and reset entries
  clk: renesas: r9a07g044: Add POEG clock and reset entries
  clk: renesas: r9a07g044: Add GPT clock and reset entry
parents f2906aa8 080bcd8d

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

+3 −4
Original line number Diff line number Diff line
@@ -45,10 +45,9 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a0*-cpg.h>

        <dt-bindings/clock/r9a0*-cpg.h>,

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or

        <dt-bindings/clock/r9a09g011-cpg.h>.

        a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.

    const: 2



  '#power-domain-cells':
@@ -62,7 +61,7 @@ properties: 
  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.

      <dt-bindings/clock/r9a0*-cpg.h>.

    const: 1



required:

drivers/clk/renesas/clk-r8a73a4.c

+11 −11
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
struct r8a73a4_cpg {

	struct clk_onecell_data data;

	spinlock_t lock;

	void __iomem *reg;

};



#define CPG_CKSCR	0xc0
@@ -59,7 +58,7 @@ static const struct clk_div_table div4_div_table[] = { 


static struct clk * __init

r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,

			     const char *name)

			   void __iomem *base, const char *name)

{

	const struct clk_div_table *table = NULL;

	const char *parent_name;
@@ -69,7 +68,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 




	if (!strcmp(name, "main")) {

		u32 ckscr = readl(cpg->reg + CPG_CKSCR);

		u32 ckscr = readl(base + CPG_CKSCR);



		switch ((ckscr >> 28) & 3) {

		case 0:	/* extal1 */
@@ -93,14 +92,14 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
		 * clock implementation and we currently have no need to change

		 * the multiplier value.

		 */

		u32 value = readl(cpg->reg + CPG_PLL0CR);

		u32 value = readl(base + CPG_PLL0CR);



		parent_name = "main";

		mult = ((value >> 24) & 0x7f) + 1;

		if (value & BIT(20))

			div = 2;

	} else if (!strcmp(name, "pll1")) {

		u32 value = readl(cpg->reg + CPG_PLL1CR);

		u32 value = readl(base + CPG_PLL1CR);



		parent_name = "main";

		/* XXX: enable bit? */
@@ -123,7 +122,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
		default:

			return ERR_PTR(-EINVAL);

		}

		value = readl(cpg->reg + cr);

		value = readl(base + cr);

		switch ((value >> 5) & 7) {

		case 0:

			parent_name = "main";
@@ -159,7 +158,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
			shift = 0;

		}

		div *= 32;

		mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);

		mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);

	} else {

		struct div4_clk *c;
@@ -181,7 +180,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
						 mult, div);

	} else {

		return clk_register_divider_table(NULL, name, parent_name, 0,

						  cpg->reg + reg, shift, 4, 0,

						  base + reg, shift, 4, 0,

						  table, &cpg->lock);

	}

}
@@ -189,6 +188,7 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
static void __init r8a73a4_cpg_clocks_init(struct device_node *np)

{

	struct r8a73a4_cpg *cpg;

	void __iomem *base;

	struct clk **clks;

	unsigned int i;

	int num_clks;
@@ -213,8 +213,8 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np) 
	cpg->data.clks = clks;

	cpg->data.clk_num = num_clks;



	cpg->reg = of_iomap(np, 0);

	if (WARN_ON(cpg->reg == NULL))

	base = of_iomap(np, 0);

	if (WARN_ON(base == NULL))

		return;



	for (i = 0; i < num_clks; ++i) {
@@ -224,7 +224,7 @@ static void __init r8a73a4_cpg_clocks_init(struct device_node *np) 
		of_property_read_string_index(np, "clock-output-names", i,

					      &name);



		clk = r8a73a4_cpg_register_clock(np, cpg, name);

		clk = r8a73a4_cpg_register_clock(np, cpg, base, name);

		if (IS_ERR(clk))

			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",

			       __func__, np, name, PTR_ERR(clk));

drivers/clk/renesas/clk-r8a7740.c

+10 −10
Original line number Diff line number Diff line
@@ -18,7 +18,6 @@ 
struct r8a7740_cpg {

	struct clk_onecell_data data;

	spinlock_t lock;

	void __iomem *reg;

};



#define CPG_FRQCRA	0x00
@@ -61,7 +60,7 @@ static u32 cpg_mode __initdata; 


static struct clk * __init

r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,

			     const char *name)

			   void __iomem *base, const char *name)

{

	const struct clk_div_table *table = NULL;

	const char *parent_name;
@@ -96,20 +95,20 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 
		 * clock implementation and we currently have no need to change

		 * the multiplier value.

		 */

		u32 value = readl(cpg->reg + CPG_FRQCRC);

		u32 value = readl(base + CPG_FRQCRC);

		parent_name = "system";

		mult = ((value >> 24) & 0x7f) + 1;

	} else if (!strcmp(name, "pllc1")) {

		u32 value = readl(cpg->reg + CPG_FRQCRA);

		u32 value = readl(base + CPG_FRQCRA);

		parent_name = "system";

		mult = ((value >> 24) & 0x7f) + 1;

		div = 2;

	} else if (!strcmp(name, "pllc2")) {

		u32 value = readl(cpg->reg + CPG_PLLC2CR);

		u32 value = readl(base + CPG_PLLC2CR);

		parent_name = "system";

		mult = ((value >> 24) & 0x3f) + 1;

	} else if (!strcmp(name, "usb24s")) {

		u32 value = readl(cpg->reg + CPG_USBCKCR);

		u32 value = readl(base + CPG_USBCKCR);

		if (value & BIT(7))

			/* extal2 */

			parent_name = of_clk_get_parent_name(np, 1);
@@ -137,7 +136,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 
						 mult, div);

	} else {

		return clk_register_divider_table(NULL, name, parent_name, 0,

						  cpg->reg + reg, shift, 4, 0,

						  base + reg, shift, 4, 0,

						  table, &cpg->lock);

	}

}
@@ -145,6 +144,7 @@ r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg, 
static void __init r8a7740_cpg_clocks_init(struct device_node *np)

{

	struct r8a7740_cpg *cpg;

	void __iomem *base;

	struct clk **clks;

	unsigned int i;

	int num_clks;
@@ -172,8 +172,8 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) 
	cpg->data.clks = clks;

	cpg->data.clk_num = num_clks;



	cpg->reg = of_iomap(np, 0);

	if (WARN_ON(cpg->reg == NULL))

	base = of_iomap(np, 0);

	if (WARN_ON(base == NULL))

		return;



	for (i = 0; i < num_clks; ++i) {
@@ -183,7 +183,7 @@ static void __init r8a7740_cpg_clocks_init(struct device_node *np) 
		of_property_read_string_index(np, "clock-output-names", i,

					      &name);



		clk = r8a7740_cpg_register_clock(np, cpg, name);

		clk = r8a7740_cpg_register_clock(np, cpg, base, name);

		if (IS_ERR(clk))

			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",

			       __func__, np, name, PTR_ERR(clk));

drivers/clk/renesas/clk-r8a7778.c

+9 −22
Original line number Diff line number Diff line
@@ -11,12 +11,6 @@ 
#include <linux/slab.h>

#include <linux/soc/renesas/rcar-rst.h>



struct r8a7778_cpg {

	struct clk_onecell_data data;

	spinlock_t lock;

	void __iomem *reg;

};



/* PLL multipliers per bits 11, 12, and 18 of MODEMR */

static const struct {

	unsigned long plla_mult;
@@ -47,8 +41,7 @@ static u32 cpg_mode_rates __initdata; 
static u32 cpg_mode_divs __initdata;



static struct clk * __init

r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,

			     const char *name)

r8a7778_cpg_register_clock(struct device_node *np, const char *name)

{

	if (!strcmp(name, "plla")) {

		return clk_register_fixed_factor(NULL, "plla",
@@ -77,7 +70,7 @@ r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg, 


static void __init r8a7778_cpg_clocks_init(struct device_node *np)

{

	struct r8a7778_cpg *cpg;

	struct clk_onecell_data *data;

	struct clk **clks;

	unsigned int i;

	int num_clks;
@@ -100,23 +93,17 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np) 
		return;

	}



	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);

	data = kzalloc(sizeof(*data), GFP_KERNEL);

	clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);

	if (cpg == NULL || clks == NULL) {

	if (data == NULL || clks == NULL) {

		/* We're leaking memory on purpose, there's no point in cleaning

		 * up as the system won't boot anyway.

		 */

		return;

	}



	spin_lock_init(&cpg->lock);



	cpg->data.clks = clks;

	cpg->data.clk_num = num_clks;



	cpg->reg = of_iomap(np, 0);

	if (WARN_ON(cpg->reg == NULL))

		return;

	data->clks = clks;

	data->clk_num = num_clks;



	for (i = 0; i < num_clks; ++i) {

		const char *name;
@@ -125,15 +112,15 @@ static void __init r8a7778_cpg_clocks_init(struct device_node *np) 
		of_property_read_string_index(np, "clock-output-names", i,

					      &name);



		clk = r8a7778_cpg_register_clock(np, cpg, name);

		clk = r8a7778_cpg_register_clock(np, name);

		if (IS_ERR(clk))

			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",

			       __func__, np, name, PTR_ERR(clk));

		else

			cpg->data.clks[i] = clk;

			data->clks[i] = clk;

	}



	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);

	of_clk_add_provider(np, of_clk_src_onecell_get, data);



	cpg_mstp_add_clk_domain(np);

}

drivers/clk/renesas/clk-r8a7779.c

+9 −18
Original line number Diff line number Diff line
@@ -21,12 +21,6 @@ 


#define CPG_NUM_CLOCKS			(R8A7779_CLK_OUT + 1)



struct r8a7779_cpg {

	struct clk_onecell_data data;

	spinlock_t lock;

	void __iomem *reg;

};



/* -----------------------------------------------------------------------------

 * CPG Clock Data

 */
@@ -87,7 +81,7 @@ static const unsigned int cpg_plla_mult[4] __initconst = { 42, 48, 56, 64 }; 
 */



static struct clk * __init

r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,

r8a7779_cpg_register_clock(struct device_node *np,

			   const struct cpg_clk_config *config,

			   unsigned int plla_mult, const char *name)

{
@@ -119,7 +113,7 @@ r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg, 
static void __init r8a7779_cpg_clocks_init(struct device_node *np)

{

	const struct cpg_clk_config *config;

	struct r8a7779_cpg *cpg;

	struct clk_onecell_data *data;

	struct clk **clks;

	unsigned int i, plla_mult;

	int num_clks;
@@ -134,19 +128,17 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) 
		return;

	}



	cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);

	data = kzalloc(sizeof(*data), GFP_KERNEL);

	clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);

	if (cpg == NULL || clks == NULL) {

	if (data == NULL || clks == NULL) {

		/* We're leaking memory on purpose, there's no point in cleaning

		 * up as the system won't boot anyway.

		 */

		return;

	}



	spin_lock_init(&cpg->lock);



	cpg->data.clks = clks;

	cpg->data.clk_num = num_clks;

	data->clks = clks;

	data->clk_num = num_clks;



	config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];

	plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
@@ -158,16 +150,15 @@ static void __init r8a7779_cpg_clocks_init(struct device_node *np) 
		of_property_read_string_index(np, "clock-output-names", i,

					      &name);



		clk = r8a7779_cpg_register_clock(np, cpg, config,

						 plla_mult, name);

		clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);

		if (IS_ERR(clk))

			pr_err("%s: failed to register %pOFn %s clock (%ld)\n",

			       __func__, np, name, PTR_ERR(clk));

		else

			cpg->data.clks[i] = clk;

			data->clks[i] = clk;

	}



	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);

	of_clk_add_provider(np, of_clk_src_onecell_get, data);



	cpg_mstp_add_clk_domain(np);

}