Commit d3762a47 authored by Fabio Estevam's avatar Fabio Estevam Committed by Shawn Guo
Browse files

arm64: dts: imx8m: Add the ENET PPS interrupt 



The i.MX8M SoCs have a fourth ENET interrupt dedicated to PPS (Pulse Per
Second). Add support for it.

Suggested-by: default avatarRogerio Nunes <rogerio.nunes@nxp.com>
Signed-off-by: default avatarFabio Estevam <festevam@gmail.com>
Reviewed-by: default avatarFugang Duan <fugang.duan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 14e292fc

arch/arm64/boot/dts/freescale/imx8mm.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -854,7 +854,8 @@ 
				reg = <0x30be0000 0x10000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,

					 <&clk IMX8MM_CLK_ENET1_ROOT>,

					 <&clk IMX8MM_CLK_ENET_TIMER>,

arch/arm64/boot/dts/freescale/imx8mn.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -741,7 +741,8 @@ 
				reg = <0x30be0000 0x10000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,

					 <&clk IMX8MN_CLK_ENET1_ROOT>,

					 <&clk IMX8MN_CLK_ENET_TIMER>,

arch/arm64/boot/dts/freescale/imx8mp.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -713,7 +713,8 @@ 
				reg = <0x30be0000 0x10000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,

					 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,

					 <&clk IMX8MP_CLK_ENET_TIMER>,

arch/arm64/boot/dts/freescale/imx8mq.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1031,7 +1031,8 @@ 
				reg = <0x30be0000 0x10000>;

				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,

				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,

				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;

					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,

					     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,

				         <&clk IMX8MQ_CLK_ENET1_ROOT>,

				         <&clk IMX8MQ_CLK_ENET_TIMER>,