Commit d36207b8 authored by Ahmad Fatoum's avatar Ahmad Fatoum Committed by Abel Vesa
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clk: imx8m: fix clock tree update of TF-A managed clocks 



On the i.MX8M*, the TF-A exposes a SiP (Silicon Provider) service
for DDR frequency scaling. The imx8m-ddrc-devfreq driver calls the
SiP and then does clk_set_parent on the DDR muxes to synchronize
the clock tree.

Since 936c3836 ("clk: imx: fix composite peripheral flags"),
these TF-A managed muxes have SET_PARENT_GATE set, which results
in imx8m-ddrc-devfreq's clk_set_parent after SiP failing with -EBUSY:

	echo 25000000 > userspace/set_freq
	imx8m-ddrc-devfreq 3d400000.memory-controller: failed to set
		dram_apb parent: -16

Fix this by adding a new i.MX composite flag for firmware managed
clocks, which clears SET_PARENT_GATE.

This is safe to do, because updating the Linux clock tree to reflect
reality will always be glitch-free.

Fixes: 936c3836 ("clk: imx: fix composite peripheral flags")
Signed-off-by: default avatarAhmad Fatoum <a.fatoum@pengutronix.de>
Reviewed-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20210810151432.9228-1-a.fatoum@pengutronix.de


Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
parent fb549644

drivers/clk/imx/clk-composite-8m.c

+2 −1
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, 
		div->width = PCG_PREDIV_WIDTH;

		divider_ops = &imx8m_clk_composite_divider_ops;

		mux_ops = &clk_mux_ops;

		if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))

			flags |= CLK_SET_PARENT_GATE;

	}

drivers/clk/imx/clk-imx8mm.c

+4 −3
Original line number Diff line number Diff line
@@ -470,10 +470,11 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) 


	/*

	 * DRAM clocks are manipulated from TF-A outside clock framework.

	 * Mark with GET_RATE_NOCACHE to always read div value from hardware

	 * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE

	 * as div value should always be read from hardware

	 */

	hws[IMX8MM_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);

	hws[IMX8MM_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mm_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);

	hws[IMX8MM_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mm_dram_alt_sels, base + 0xa000);

	hws[IMX8MM_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mm_dram_apb_sels, base + 0xa080);



	/* IP */

	hws[IMX8MM_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mm_vpu_g1_sels, base + 0xa100);

drivers/clk/imx/clk-imx8mn.c

+4 −3
Original line number Diff line number Diff line
@@ -453,10 +453,11 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) 


	/*

	 * DRAM clocks are manipulated from TF-A outside clock framework.

	 * Mark with GET_RATE_NOCACHE to always read div value from hardware

	 * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE

	 * as div value should always be read from hardware

	 */

	hws[IMX8MN_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);

	hws[IMX8MN_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mn_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);

	hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000);

	hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080);



	hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500);

	hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600);

drivers/clk/imx/clk-imx8mq.c

+4 −3
Original line number Diff line number Diff line
@@ -449,11 +449,12 @@ static int imx8mq_clocks_probe(struct platform_device *pdev) 


	/*

	 * DRAM clocks are manipulated from TF-A outside clock framework.

	 * Mark with GET_RATE_NOCACHE to always read div value from hardware

	 * The fw_managed helper sets GET_RATE_NOCACHE and clears SET_PARENT_GATE

	 * as div value should always be read from hardware

	 */

	hws[IMX8MQ_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mq_dram_core_sels, ARRAY_SIZE(imx8mq_dram_core_sels), CLK_IS_CRITICAL);

	hws[IMX8MQ_CLK_DRAM_ALT] = __imx8m_clk_hw_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000, CLK_GET_RATE_NOCACHE);

	hws[IMX8MQ_CLK_DRAM_APB] = __imx8m_clk_hw_composite("dram_apb", imx8mq_dram_apb_sels, base + 0xa080, CLK_IS_CRITICAL | CLK_GET_RATE_NOCACHE);

	hws[IMX8MQ_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mq_dram_alt_sels, base + 0xa000);

	hws[IMX8MQ_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mq_dram_apb_sels, base + 0xa080);



	/* IP */

	hws[IMX8MQ_CLK_VPU_G1] = imx8m_clk_hw_composite("vpu_g1", imx8mq_vpu_g1_sels, base + 0xa100);

drivers/clk/imx/clk.h

+14 −2
Original line number Diff line number Diff line
@@ -532,6 +532,7 @@ struct clk_hw *imx_clk_hw_cpu(const char *name, const char *parent_name, 


#define IMX_COMPOSITE_CORE		BIT(0)

#define IMX_COMPOSITE_BUS		BIT(1)

#define IMX_COMPOSITE_FW_MANAGED	BIT(2)



struct clk_hw *imx8m_clk_hw_composite_flags(const char *name,

					    const char * const *parent_names,
@@ -567,6 +568,17 @@ struct clk_hw *imx8m_clk_hw_composite_flags(const char *name, 
		ARRAY_SIZE(parent_names), reg, 0, \

		flags | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)



#define __imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, flags) \

	imx8m_clk_hw_composite_flags(name, parent_names, \

		ARRAY_SIZE(parent_names), reg, IMX_COMPOSITE_FW_MANAGED, \

		flags | CLK_GET_RATE_NOCACHE | CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)



#define imx8m_clk_hw_fw_managed_composite(name, parent_names, reg) \

	__imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, 0)



#define imx8m_clk_hw_fw_managed_composite_critical(name, parent_names, reg) \

	__imx8m_clk_hw_fw_managed_composite(name, parent_names, reg, CLK_IS_CRITICAL)



#define __imx8m_clk_composite(name, parent_names, reg, flags) \

	to_clk(__imx8m_clk_hw_composite(name, parent_names, reg, flags))