Commit d2f2f1d1 authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Joerg Roedel
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dt-bindings: iommu: arm,smmu-v3: Relax order of interrupt names



The QEMU devicetree uses a different order for SMMUv3 interrupt names,
and there isn't a good reason for enforcing a specific order. Since all
interrupt lines are optional, operating systems should not expect a
fixed interrupt array layout; they should instead match each interrupt
to its name individually. Besides, as a result of commit e4783856
("dt-bindings: iommu: arm,smmu-v3: make PRI IRQ optional"), "cmdq-sync"
and "priq" are already permutable. Relax the interrupt-names array
entirely by allowing any permutation, incidentally making the schema
more readable.

Note that dt-validate won't allow duplicate names here so we don't need
to specify maxItems or add additional checks, it's quite neat.

Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe@linaro.org>
Acked-by: default avatarWill Deacon <will@kernel.org>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220916133145.1910549-1-jean-philippe@linaro.org


Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 7e18e42e
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+5 −10
Original line number Diff line number Diff line
@@ -39,16 +39,11 @@ properties:
          any others.
      - minItems: 1
        items:
          - enum:
          enum:
            - eventq      # Event Queue not empty
            - gerror      # Global Error activated
          - const: gerror
          - enum:
            - cmdq-sync   # CMD_SYNC complete
            - priq        # PRI Queue not empty
          - enum:
              - cmdq-sync
              - priq

  '#iommu-cells':
    const: 1