Loading drivers/gpu/drm/i915/intel_pm.c +28 −22 Original line number Diff line number Diff line Loading @@ -7358,21 +7358,20 @@ void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) pm_runtime_disable(device); } /* Set up chip specific power management-related functions */ void intel_init_pm(struct drm_device *dev) static void intel_init_fbc(struct drm_i915_private *dev_priv) { struct drm_i915_private *dev_priv = dev->dev_private; if (!HAS_FBC(dev_priv)) return; if (HAS_FBC(dev)) { if (INTEL_INFO(dev)->gen >= 7) { if (INTEL_INFO(dev_priv)->gen >= 7) { dev_priv->display.fbc_enabled = ironlake_fbc_enabled; dev_priv->display.enable_fbc = gen7_enable_fbc; dev_priv->display.disable_fbc = ironlake_disable_fbc; } else if (INTEL_INFO(dev)->gen >= 5) { } else if (INTEL_INFO(dev_priv)->gen >= 5) { dev_priv->display.fbc_enabled = ironlake_fbc_enabled; dev_priv->display.enable_fbc = ironlake_enable_fbc; dev_priv->display.disable_fbc = ironlake_disable_fbc; } else if (IS_GM45(dev)) { } else if (IS_GM45(dev_priv)) { dev_priv->display.fbc_enabled = g4x_fbc_enabled; dev_priv->display.enable_fbc = g4x_enable_fbc; dev_priv->display.disable_fbc = g4x_disable_fbc; Loading @@ -7386,6 +7385,13 @@ void intel_init_pm(struct drm_device *dev) } } /* Set up chip specific power management-related functions */ void intel_init_pm(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; intel_init_fbc(dev_priv); /* For cxsr */ if (IS_PINEVIEW(dev)) i915_pineview_get_mem_freq(dev); Loading Loading
drivers/gpu/drm/i915/intel_pm.c +28 −22 Original line number Diff line number Diff line Loading @@ -7358,21 +7358,20 @@ void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) pm_runtime_disable(device); } /* Set up chip specific power management-related functions */ void intel_init_pm(struct drm_device *dev) static void intel_init_fbc(struct drm_i915_private *dev_priv) { struct drm_i915_private *dev_priv = dev->dev_private; if (!HAS_FBC(dev_priv)) return; if (HAS_FBC(dev)) { if (INTEL_INFO(dev)->gen >= 7) { if (INTEL_INFO(dev_priv)->gen >= 7) { dev_priv->display.fbc_enabled = ironlake_fbc_enabled; dev_priv->display.enable_fbc = gen7_enable_fbc; dev_priv->display.disable_fbc = ironlake_disable_fbc; } else if (INTEL_INFO(dev)->gen >= 5) { } else if (INTEL_INFO(dev_priv)->gen >= 5) { dev_priv->display.fbc_enabled = ironlake_fbc_enabled; dev_priv->display.enable_fbc = ironlake_enable_fbc; dev_priv->display.disable_fbc = ironlake_disable_fbc; } else if (IS_GM45(dev)) { } else if (IS_GM45(dev_priv)) { dev_priv->display.fbc_enabled = g4x_fbc_enabled; dev_priv->display.enable_fbc = g4x_enable_fbc; dev_priv->display.disable_fbc = g4x_disable_fbc; Loading @@ -7386,6 +7385,13 @@ void intel_init_pm(struct drm_device *dev) } } /* Set up chip specific power management-related functions */ void intel_init_pm(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; intel_init_fbc(dev_priv); /* For cxsr */ if (IS_PINEVIEW(dev)) i915_pineview_get_mem_freq(dev); Loading