Commit d2aaf040 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events: Update Intel ivytown 

Events are updated to v22 the core metrics are based on TMA 4.4 full.

Use script at:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py
with updates at:
https://github.com/captain5050/event-converter-for-linux-perf



Updates include:
 - Rename of topdown TMA metrics from Frontend_Bound to tma_frontend_bound.
 - _SMT suffix metrics are dropped as the #SMT_On and #EBS_Mode are
   correctly expanded in the single main metric.
 - Addition of all 6 levels of TMA metrics. Child metrics are placed in
   a group named after their parent allowing children of a metric to
   be easily measured using the metric name with a _group suffix.
 - ## and ##? operators are correctly expanded.
 - The locate-with column is added to the long description describing
   a sampling event.
 - Metrics are written in terms of other metrics to reduce the
   expression size and increase readability.

Tested with 'perf test':
 10: PMU events                                                      :
 10.1: PMU event table sanity                                        : Ok
 10.2: PMU event map aliases                                         : Ok
 10.3: Parsing of PMU event table metrics                            : Ok
 10.4: Parsing of PMU event table metrics with fake PMUs             : Ok

Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Ahmad Yasin <ahmad.yasin@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Florian Fischer <florian.fischer@muhq.space>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Kajol Jain <kjain@linux.ibm.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Kshipra Bopardikar <kshipra.bopardikar@intel.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Miaoqian Lin <linmq006@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221004021612.325521-17-irogers@google.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 3bd2d211

tools/perf/pmu-events/arch/x86/ivytown/cache.json

+2 −2
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ 
        "UMask": "0x2"

    },

    {

        "BriefDescription": "L1D miss oustandings duration in cycles",

        "BriefDescription": "L1D miss outstanding duration in cycles",

        "Counter": "2",

        "CounterHTOff": "2",

        "EventCode": "0x48",
@@ -658,7 +658,7 @@ 
        "UMask": "0x8"

    },

    {

        "BriefDescription": "Cacheable and noncachaeble code read requests",

        "BriefDescription": "Cacheable and noncacheable code read requests",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0xB0",

tools/perf/pmu-events/arch/x86/ivytown/frontend.json

+9 −9
Original line number Diff line number Diff line
@@ -176,41 +176,41 @@ 
        "UMask": "0x4"

    },

    {

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_CYCLES",

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "SampleAfterValue": "2000003",

        "UMask": "0x30"

    },

    {

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_CYCLES",

        "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",

        "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.",

        "SampleAfterValue": "2000003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",

        "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EdgeDetect": "1",

        "EventCode": "0x79",

        "EventName": "IDQ.MS_DSB_OCCUR",

        "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",

        "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is busy.",

        "SampleAfterValue": "2000003",

        "UMask": "0x10"

    },

    {

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",
@@ -220,7 +220,7 @@ 
        "UMask": "0x10"

    },

    {

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",
@@ -242,7 +242,7 @@ 
        "UMask": "0x30"

    },

    {

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",

        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy",

        "Counter": "0,1,2,3",

        "CounterHTOff": "0,1,2,3,4,5,6,7",

        "EventCode": "0x79",

tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json

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tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json

+29 −29

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tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json

+42 −42

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