Commit d294ad82 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'net-ll_temac-cleanup-for-clearing-static-warnings' 

Haoyue Xu says:

====================
net: ll_temac: Cleanup for clearing static warnings

Most static warnings are detected by Checkpatch.pl, mainly about:
(1) #1: About the comments.
(2) #2: About function name in a string.
(3) #3: About the open parenthesis.
(4) #4: About the else branch.
(6) #6: About trailing statements.
(7) #5,#7: About blank lines and spaces.
====================

Link: https://lore.kernel.org/r/20220917103843.526877-1-xuhaoyue1@hisilicon.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents d57aae2e 7fe85bb3

drivers/net/ethernet/xilinx/ll_temac.h

+95 −86
Original line number Diff line number Diff line
@@ -21,36 +21,45 @@ 
/*  Configuration options */



/*  Accept all incoming packets.

 *  This option defaults to disabled (cleared) */

 *  This option defaults to disabled (cleared)

 */

#define XTE_OPTION_PROMISC                      (1 << 0)

/*  Jumbo frame support for Tx & Rx.

 *  This option defaults to disabled (cleared) */

 *  This option defaults to disabled (cleared)

 */

#define XTE_OPTION_JUMBO                        (1 << 1)

/*  VLAN Rx & Tx frame support.

 *  This option defaults to disabled (cleared) */

 *  This option defaults to disabled (cleared)

 */

#define XTE_OPTION_VLAN                         (1 << 2)

/*  Enable recognition of flow control frames on Rx

 *  This option defaults to enabled (set) */

 *  This option defaults to enabled (set)

 */

#define XTE_OPTION_FLOW_CONTROL                 (1 << 4)

/*  Strip FCS and PAD from incoming frames.

 *  Note: PAD from VLAN frames is not stripped.

 *  This option defaults to disabled (set) */

 *  This option defaults to disabled (set)

 */

#define XTE_OPTION_FCS_STRIP                    (1 << 5)

/*  Generate FCS field and add PAD automatically for outgoing frames.

 *  This option defaults to enabled (set) */

 *  This option defaults to enabled (set)

 */

#define XTE_OPTION_FCS_INSERT                   (1 << 6)

/*  Enable Length/Type error checking for incoming frames. When this option is

set, the MAC will filter frames that have a mismatched type/length field

and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these

types of frames are encountered. When this option is cleared, the MAC will

allow these types of frames to be received.

This option defaults to enabled (set) */

 *  set, the MAC will filter frames that have a mismatched type/length field

 *  and if XTE_OPTION_REPORT_RXERR is set, the user is notified when these

 *  types of frames are encountered. When this option is cleared, the MAC will

 *  allow these types of frames to be received.

 *  This option defaults to enabled (set)

 */

#define XTE_OPTION_LENTYPE_ERR                  (1 << 7)

/*  Enable the transmitter.

 *  This option defaults to enabled (set) */

 *  This option defaults to enabled (set)

 */

#define XTE_OPTION_TXEN                         (1 << 11)

/*  Enable the receiver

*   This option defaults to enabled (set) */

 *  This option defaults to enabled (set)

 */

#define XTE_OPTION_RXEN                         (1 << 12)



/*  Default options set when device is initialized or reset */
@@ -68,17 +77,17 @@ This option defaults to enabled (set) */ 
#define TX_TAILDESC_PTR     0x04            /* rw */

#define TX_CHNL_CTRL        0x05            /* rw */

/*

 0:7      24:31       IRQTimeout

 8:15     16:23       IRQCount

 16:20    11:15       Reserved

 21       10          0

 22       9           UseIntOnEnd

 23       8           LdIRQCnt

 24       7           IRQEn

 25:28    3:6         Reserved

 29       2           IrqErrEn

 30       1           IrqDlyEn

 31       0           IrqCoalEn

 *  0:7      24:31       IRQTimeout

 *  8:15     16:23       IRQCount

 *  16:20    11:15       Reserved

 *  21       10          0

 *  22       9           UseIntOnEnd

 *  23       8           LdIRQCnt

 *  24       7           IRQEn

 *  25:28    3:6         Reserved

 *  29       2           IrqErrEn

 *  30       1           IrqDlyEn

 *  31       0           IrqCoalEn

 */

#define CHNL_CTRL_IRQ_IOE       (1 << 9)

#define CHNL_CTRL_IRQ_EN        (1 << 7)
@@ -87,34 +96,34 @@ This option defaults to enabled (set) */ 
#define CHNL_CTRL_IRQ_COAL_EN   (1 << 0)

#define TX_IRQ_REG          0x06            /* rw */

/*

  0:7      24:31       DltTmrValue

 8:15     16:23       ClscCntrValue

 16:17    14:15       Reserved

 18:21    10:13       ClscCnt

 22:23    8:9         DlyCnt

 24:28    3::7        Reserved

 29       2           ErrIrq

 30       1           DlyIrq

 31       0           CoalIrq

 *  0:7      24:31       DltTmrValue

 *  8:15     16:23       ClscCntrValue

 *  16:17    14:15       Reserved

 *  18:21    10:13       ClscCnt

 *  22:23    8:9         DlyCnt

 *  24:28    3::7        Reserved

 *  29       2           ErrIrq

 *  30       1           DlyIrq

 *  31       0           CoalIrq

 */

#define TX_CHNL_STS         0x07            /* r */

/*

   0:9      22:31   Reserved

 10       21      TailPErr

 11       20      CmpErr

 12       19      AddrErr

 13       18      NxtPErr

 14       17      CurPErr

 15       16      BsyWr

 16:23    8:15    Reserved

 24       7       Error

 25       6       IOE

 26       5       SOE

 27       4       Cmplt

 28       3       SOP

 29       2       EOP

 30       1       EngBusy

 31       0       Reserved

 *  0:9      22:31   Reserved

 *  10       21      TailPErr

 *  11       20      CmpErr

 *  12       19      AddrErr

 *  13       18      NxtPErr

 *  14       17      CurPErr

 *  15       16      BsyWr

 *  16:23    8:15    Reserved

 *  24       7       Error

 *  25       6       IOE

 *  26       5       SOE

 *  27       4       Cmplt

 *  28       3       SOP

 *  29       2       EOP

 *  30       1       EngBusy

 *  31       0       Reserved

 */



#define RX_NXTDESC_PTR      0x08            /* r */
@@ -124,17 +133,17 @@ This option defaults to enabled (set) */ 
#define RX_TAILDESC_PTR     0x0c            /* rw */

#define RX_CHNL_CTRL        0x0d            /* rw */

/*

 0:7      24:31       IRQTimeout

 8:15     16:23       IRQCount

 16:20    11:15       Reserved

 21       10          0

 22       9           UseIntOnEnd

 23       8           LdIRQCnt

 24       7           IRQEn

 25:28    3:6         Reserved

 29       2           IrqErrEn

 30       1           IrqDlyEn

 31       0           IrqCoalEn

 *  0:7      24:31       IRQTimeout

 *  8:15     16:23       IRQCount

 *  16:20    11:15       Reserved

 *  21       10          0

 *  22       9           UseIntOnEnd

 *  23       8           LdIRQCnt

 *  24       7           IRQEn

 *  25:28    3:6         Reserved

 *  29       2           IrqErrEn

 *  30       1           IrqDlyEn

 *  31       0           IrqCoalEn

 */

#define RX_IRQ_REG          0x0e            /* rw */

#define IRQ_COAL        (1 << 0)
@@ -142,12 +151,12 @@ This option defaults to enabled (set) */ 
#define IRQ_ERR         (1 << 2)

#define IRQ_DMAERR      (1 << 7)            /* this is not documented ??? */

/*

 0:7      24:31       DltTmrValue

 8:15     16:23       ClscCntrValue

 16:17    14:15       Reserved

 18:21    10:13       ClscCnt

 22:23    8:9         DlyCnt

 24:28    3::7        Reserved

 *  0:7      24:31       DltTmrValue

 *  8:15     16:23       ClscCntrValue

 *  16:17    14:15       Reserved

 *  18:21    10:13       ClscCnt

 *  22:23    8:9         DlyCnt

 *  24:28    3::7        Reserved

 */

#define RX_CHNL_STS         0x0f        /* r */

#define CHNL_STS_ENGBUSY    (1 << 1)
@@ -165,22 +174,22 @@ This option defaults to enabled (set) */ 
#define CHNL_STS_CMPERR     (1 << 20)

#define CHNL_STS_TAILERR    (1 << 21)

/*

 0:9      22:31   Reserved

 10       21      TailPErr

 11       20      CmpErr

 12       19      AddrErr

 13       18      NxtPErr

 14       17      CurPErr

 15       16      BsyWr

 16:23    8:15    Reserved

 24       7       Error

 25       6       IOE

 26       5       SOE

 27       4       Cmplt

 28       3       SOP

 29       2       EOP

 30       1       EngBusy

 31       0       Reserved

 *  0:9      22:31   Reserved

 *  10       21      TailPErr

 *  11       20      CmpErr

 *  12       19      AddrErr

 *  13       18      NxtPErr

 *  14       17      CurPErr

 *  15       16      BsyWr

 *  16:23    8:15    Reserved

 *  24       7       Error

 *  25       6       IOE

 *  26       5       SOE

 *  27       4       Cmplt

 *  28       3       SOP

 *  29       2       EOP

 *  30       1       EngBusy

 *  31       0       Reserved

 */



#define DMA_CONTROL_REG             0x10            /* rw */

drivers/net/ethernet/xilinx/ll_temac_main.c

+35 −30
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ int temac_indirect_busywait(struct temac_local *lp) 
	spin_until_cond(hard_acs_rdy_or_timeout(lp, timeout));

	if (WARN_ON(!hard_acs_rdy(lp)))

		return -ETIMEDOUT;

	else



	return 0;

}
@@ -307,12 +307,10 @@ static void temac_dma_bd_release(struct net_device *ndev) 
	for (i = 0; i < lp->rx_bd_num; i++) {

		if (!lp->rx_skb[i])

			break;

		else {

		dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,

				 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);

		dev_kfree_skb(lp->rx_skb[i]);

	}

	}

	if (lp->rx_bd_v)

		dma_free_coherent(ndev->dev.parent,

				  sizeof(*lp->rx_bd_v) * lp->rx_bd_num,
@@ -430,7 +428,8 @@ static void temac_do_set_mac_address(struct net_device *ndev) 
				    (ndev->dev_addr[2] << 16) |

				    (ndev->dev_addr[3] << 24));

	/* There are reserved bits in EUAW1

	 * so don't affect them Set MAC bits [47:32] in EUAW1 */

	 * so don't affect them Set MAC bits [47:32] in EUAW1

	 */

	temac_indirect_out32_locked(lp, XTE_UAW1_OFFSET,

				    (ndev->dev_addr[4] & 0x000000ff) |

				    (ndev->dev_addr[5] << 8));
@@ -641,7 +640,7 @@ static void temac_device_reset(struct net_device *ndev) 
		udelay(1);

		if (--timeout == 0) {

			dev_err(&ndev->dev,

				"temac_device_reset RX reset timeout!!\n");

				"%s RX reset timeout!!\n", __func__);

			break;

		}

	}
@@ -653,7 +652,7 @@ static void temac_device_reset(struct net_device *ndev) 
		udelay(1);

		if (--timeout == 0) {

			dev_err(&ndev->dev,

				"temac_device_reset TX reset timeout!!\n");

				"%s TX reset timeout!!\n", __func__);

			break;

		}

	}
@@ -672,7 +671,7 @@ static void temac_device_reset(struct net_device *ndev) 
		udelay(1);

		if (--timeout == 0) {

			dev_err(&ndev->dev,

				"temac_device_reset DMA reset timeout!!\n");

				"%s DMA reset timeout!!\n", __func__);

			break;

		}

	}
@@ -680,7 +679,7 @@ static void temac_device_reset(struct net_device *ndev) 


	if (temac_dma_bd_init(ndev)) {

		dev_err(&ndev->dev,

				"temac_device_reset descriptor allocation failed\n");

			"%s descriptor allocation failed\n", __func__);

	}



	spin_lock_irqsave(lp->indirect_lock, flags);
@@ -691,7 +690,8 @@ static void temac_device_reset(struct net_device *ndev) 
	spin_unlock_irqrestore(lp->indirect_lock, flags);



	/* Sync default options with HW

	 * but leave receiver and transmitter disabled.  */

	 * but leave receiver and transmitter disabled.

	 */

	temac_setoptions(ndev,

			 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
@@ -723,9 +723,15 @@ static void temac_adjust_link(struct net_device *ndev) 
		mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;



		switch (phy->speed) {

		case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;

		case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;

		case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;

		case SPEED_1000:

			mii_speed |= XTE_EMCFG_LINKSPD_1000;

			break;

		case SPEED_100:

			mii_speed |= XTE_EMCFG_LINKSPD_100;

			break;

		case SPEED_10:

			mii_speed |= XTE_EMCFG_LINKSPD_10;

			break;

		}



		/* Write new speed setting out to TEMAC */
@@ -1007,7 +1013,6 @@ static void ll_temac_recv(struct net_device *ndev) 
		if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&

		    (skb->protocol == htons(ETH_P_IP)) &&

		    (skb->len > 64)) {



			/* Convert from device endianness (be32) to cpu

			 * endianness, and if necessary swap the bytes

			 * (back) for proper IP checksum byte order

drivers/net/ethernet/xilinx/ll_temac_mdio.c

+4 −2
Original line number Diff line number Diff line
@@ -29,7 +29,8 @@ static int temac_mdio_read(struct mii_bus *bus, int phy_id, int reg) 


	/* Write the PHY address to the MIIM Access Initiator register.

	 * When the transfer completes, the PHY register value will appear

	 * in the LSW0 register */

	 * in the LSW0 register

	 */

	spin_lock_irqsave(lp->indirect_lock, flags);

	temac_iow(lp, XTE_LSW0_OFFSET, (phy_id << 5) | reg);

	rc = temac_indirect_in32_locked(lp, XTE_MIIMAI_OFFSET);
@@ -88,7 +89,8 @@ int temac_mdio_setup(struct temac_local *lp, struct platform_device *pdev) 
	}



	/* Enable the MDIO bus by asserting the enable bit and writing

	 * in the clock config */

	 * in the clock config

	 */

	temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div);



	bus = devm_mdiobus_alloc(&pdev->dev);

drivers/net/ethernet/xilinx/xilinx_axienet.h

+1 −1

File changed.

Contains only whitespace changes.

drivers/net/ethernet/xilinx/xilinx_axienet_main.c

+3 −3

File changed.

Contains only whitespace changes.

drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c

+1 −1

File changed.

Contains only whitespace changes.