Commit d2857765 authored by Sandipan Das's avatar Sandipan Das Committed by Wenkuan Wang
Browse files

perf vendor events amd: Add Zen 4 memory controller events 

mainline inclusion
from mainline-v6.8-rc2
commit 346878dacc81f53667381c8f4bb5018195ca10be
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9016O


CVE: NA

--------------------------------

Make the jevents parser aware of the Unified Memory Controller (UMC) PMU
and add events taken from Section 8.2.1 "UMC Performance Monitor Events"
of the Processor Programming Reference (PPR) for AMD Family 19h Model 11h
processors. The events capture UMC command activity such as CAS, ACTIVATE,
PRECHARGE etc. while the metrics derive data bus utilization and memory
bandwidth out of these events.

Signed-off-by: default avatarSandipan Das <sandipan.das@amd.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ananth Narayan <ananth.narayan@amd.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Stephane Eranian <eranian@google.com>
Link: https://lore.kernel.org/r/e0d8a7e8ca8ee3e378d8029e80b456ac327d6419.1701238314.git.sandipan.das@amd.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: default avatarWenkuan Wang <Wenkuan.Wang@amd.com>
parent d7b1b5b5

tools/perf/pmu-events/arch/x86/amdzen4/memory-controller.json

0 → 100644
+101 −0
Original line number Diff line number Diff line 
[

  {

    "EventName": "umc_mem_clk",

    "PublicDescription": "Number of memory clock cycles.",

    "EventCode": "0x00",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.all",

    "PublicDescription": "Number of ACTIVATE commands sent.",

    "EventCode": "0x05",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.rd",

    "PublicDescription": "Number of ACTIVATE commands sent for reads.",

    "EventCode": "0x05",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_act_cmd.wr",

    "PublicDescription": "Number of ACTIVATE commands sent for writes.",

    "EventCode": "0x05",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.all",

    "PublicDescription": "Number of PRECHARGE commands sent.",

    "EventCode": "0x06",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.rd",

    "PublicDescription": "Number of PRECHARGE commands sent for reads.",

    "EventCode": "0x06",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_pchg_cmd.wr",

    "PublicDescription": "Number of PRECHARGE commands sent for writes.",

    "EventCode": "0x06",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.all",

    "PublicDescription": "Number of CAS commands sent.",

    "EventCode": "0x0a",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.rd",

    "PublicDescription": "Number of CAS commands sent for reads.",

    "EventCode": "0x0a",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_cas_cmd.wr",

    "PublicDescription": "Number of CAS commands sent for writes.",

    "EventCode": "0x0a",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.all",

    "PublicDescription": "Number of clocks used by the data bus.",

    "EventCode": "0x14",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.rd",

    "PublicDescription": "Number of clocks used by the data bus for reads.",

    "EventCode": "0x14",

    "RdWrMask": "0x1",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  },

  {

    "EventName": "umc_data_slot_clks.wr",

    "PublicDescription": "Number of clocks used by the data bus for writes.",

    "EventCode": "0x14",

    "RdWrMask": "0x2",

    "PerPkg": "1",

    "Unit": "UMCPMC"

  }

]

tools/perf/pmu-events/arch/x86/amdzen4/recommended.json

+84 −0
Original line number Diff line number Diff line
@@ -330,5 +330,89 @@ 
    "MetricGroup": "data_fabric",

    "PerPkg": "1",

    "ScaleUnit": "6.103515625e-5MiB"

  },

  {

    "MetricName": "umc_data_bus_utilization",

    "BriefDescription": "Memory controller data bus utilization.",

    "MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_cas_cmd_rate",

    "BriefDescription": "Memory controller CAS command rate.",

    "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  },

  {

    "MetricName": "umc_cas_cmd_read_ratio",

    "BriefDescription": "Ratio of memory controller CAS commands for reads.",

    "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_cas_cmd_write_ratio",

    "BriefDescription": "Ratio of memory controller CAS commands for writes.",

    "MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_mem_read_bandwidth",

    "BriefDescription": "Estimated memory read bandwidth.",

    "MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "1MB/s"

  },

  {

    "MetricName": "umc_mem_write_bandwidth",

    "BriefDescription": "Estimated memory write bandwidth.",

    "MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "1MB/s"

  },

  {

    "MetricName": "umc_mem_bandwidth",

    "BriefDescription": "Estimated combined memory bandwidth.",

    "MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "1MB/s"

  },

  {

    "MetricName": "umc_cas_cmd_read_ratio",

    "BriefDescription": "Ratio of memory controller CAS commands for reads.",

    "MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1",

    "ScaleUnit": "100%"

  },

  {

    "MetricName": "umc_cas_cmd_rate",

    "BriefDescription": "Memory controller CAS command rate.",

    "MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  },

  {

    "MetricName": "umc_activate_cmd_rate",

    "BriefDescription": "Memory controller ACTIVATE command rate.",

    "MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  },

  {

    "MetricName": "umc_precharge_cmd_rate",

    "BriefDescription": "Memory controller PRECHARGE command rate.",

    "MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",

    "MetricGroup": "memory_controller",

    "PerPkg": "1"

  }

]

tools/perf/pmu-events/jevents.py

+2 −0
Original line number Diff line number Diff line
@@ -286,6 +286,7 @@ class JsonEvent: 
          'imx8_ddr': 'imx8_ddr',

          'L3PMC': 'amd_l3',

          'DFPMC': 'amd_df',

          'UMCPMC': 'amd_umc',

          'cpu_core': 'cpu_core',

          'cpu_atom': 'cpu_atom',

          'ali_drw': 'ali_drw',
@@ -345,6 +346,7 @@ class JsonEvent: 
        ('Invert', 'inv='),

        ('SampleAfterValue', 'period='),

        ('UMask', 'umask='),

        ('RdWrMask', 'rdwrmask='),

    ]

    for key, value in event_fields:

      if key in jd and jd[key] != '0':