Commit d25f0025 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull CXL updates from Dan Williams:
 "The highlights in terms of new functionality are support for the
  standard CXL Performance Monitor definition that appeared in CXL 3.0,
  support for device sanitization (wiping all data from a device),
  secure-erase (re-keying encryption of user data), and support for
  firmware update. The firmware update support is notable as it reuses
  the simple sysfs_upload interface to just cat(1) a blob to a sysfs
  file and pipe that to the device.

  Additionally there are a substantial number of cleanups and
  reorganizations to get ready for RCH error handling (RCH == Restricted
  CXL Host == current shipping hardware generation / pre CXL-2.0
  topologies) and type-2 (accelerator / vendor specific) devices.

  For vendor specific devices they implement a subset of what the
  generic type-3 (generic memory expander) driver expects. As a result
  the rework decouples optional infrastructure from the core driver
  context.

  For RCH topologies, where the specification working group did not want
  to confuse pre-CXL-aware operating systems, many of the standard
  registers are hidden which makes support standard bus features like
  AER (PCIe Advanced Error Reporting) difficult. The rework arranges for
  the driver to help the PCI-AER core. Bjorn is on board with this
  direction but a late regression disocvery means the completion of this
  functionality needs to cook a bit longer, so it is code
  reorganizations only for now.

  Summary:

   - Add infrastructure for supporting background commands along with
     support for device sanitization and firmware update

   - Introduce a CXL performance monitoring unit driver based on the
     common definition in the specification.

   - Land some preparatory cleanup and refactoring for the anticipated
     arrival of CXL type-2 (accelerator devices) and CXL RCH (CXL-v1.1
     topology) error handling.

   - Rework CPU cache management with respect to region configuration
     (device hotplug or other dynamic changes to memory interleaving)

   - Fix region reconfiguration vs CXL decoder ordering rules"

* tag 'cxl-for-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (51 commits)
  cxl: Fix one kernel-doc comment
  cxl/pci: Use correct flag for sanitize polling
  docs: perf: Minimal introduction the the CXL PMU device and driver
  perf: CXL Performance Monitoring Unit driver
  tools/testing/cxl: add firmware update emulation to CXL memdevs
  tools/testing/cxl: Use named effects for the Command Effect Log
  tools/testing/cxl: Fix command effects for inject/clear poison
  cxl: add a firmware update mechanism using the sysfs firmware loader
  cxl/test: Add Secure Erase opcode support
  cxl/mem: Support Secure Erase
  cxl/test: Add Sanitize opcode support
  cxl/mem: Wire up Sanitization support
  cxl/mbox: Add sanitization handling machinery
  cxl/mem: Introduce security state sysfs file
  cxl/mbox: Allow for IRQ_NONE case in the isr
  Revert "cxl/port: Enable the HDM decoder capability for switch ports"
  cxl/memdev: Formalize endpoint port linkage
  cxl/pci: Unconditionally unmask 256B Flit errors
  cxl/region: Manage decoder target_type at decoder-attach time
  cxl/hdm: Default CXL_DEVTYPE_DEVMEM decoders to CXL_DECODER_DEVMEM
  ...
parents 0a1c979c fe77cc2e
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@@ -58,6 +58,54 @@ Description:
		affinity for this device.


What:		/sys/bus/cxl/devices/memX/security/state
Date:		June, 2023
KernelVersion:	v6.5
Contact:	linux-cxl@vger.kernel.org
Description:
		(RO) Reading this file will display the CXL security state for
		that device. Such states can be: 'disabled', 'sanitize', when
		a sanitization is currently underway; or those available only
		for persistent memory: 'locked', 'unlocked' or 'frozen'. This
		sysfs entry is select/poll capable from userspace to notify
		upon completion of a sanitize operation.


What:           /sys/bus/cxl/devices/memX/security/sanitize
Date:           June, 2023
KernelVersion:  v6.5
Contact:        linux-cxl@vger.kernel.org
Description:
		(WO) Write a boolean 'true' string value to this attribute to
		sanitize the device to securely re-purpose or decommission it.
		This is done by ensuring that all user data and meta-data,
		whether it resides in persistent capacity, volatile capacity,
		or the LSA, is made permanently unavailable by whatever means
		is appropriate for the media type. This functionality requires
		the device to be not be actively decoding any HPA ranges.


What            /sys/bus/cxl/devices/memX/security/erase
Date:           June, 2023
KernelVersion:  v6.5
Contact:        linux-cxl@vger.kernel.org
Description:
		(WO) Write a boolean 'true' string value to this attribute to
		secure erase user data by changing the media encryption keys for
		all user data areas of the device.


What:		/sys/bus/cxl/devices/memX/firmware/
Date:		April, 2023
KernelVersion:	v6.5
Contact:	linux-cxl@vger.kernel.org
Description:
		(RW) Firmware uploader mechanism. The different files under
		this directory can be used to upload and activate new
		firmware for CXL devices. The interfaces under this are
		documented in sysfs-class-firmware.


What:		/sys/bus/cxl/devices/*/devtype
Date:		June, 2021
KernelVersion:	v5.14
+68 −0
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.. SPDX-License-Identifier: GPL-2.0

======================================
CXL Performance Monitoring Unit (CPMU)
======================================

The CXL rev 3.0 specification provides a definition of CXL Performance
Monitoring Unit in section 13.2: Performance Monitoring.

CXL components (e.g. Root Port, Switch Upstream Port, End Point) may have
any number of CPMU instances. CPMU capabilities are fully discoverable from
the devices. The specification provides event definitions for all CXL protocol
message types and a set of additional events for things commonly counted on
CXL devices (e.g. DRAM events).

CPMU driver
===========

The CPMU driver registers a perf PMU with the name pmu_mem<X>.<Y> on the CXL bus
representing the Yth CPMU for memX.

    /sys/bus/cxl/device/pmu_mem<X>.<Y>

The associated PMU is registered as

   /sys/bus/event_sources/devices/cxl_pmu_mem<X>.<Y>

In common with other CXL bus devices, the id has no specific meaning and the
relationship to specific CXL device should be established via the device parent
of the device on the CXL bus.

PMU driver provides description of available events and filter options in sysfs.

The "format" directory describes all formats of the config (event vendor id,
group id and mask) config1 (threshold, filter enables) and config2 (filter
parameters) fields of the perf_event_attr structure.  The "events" directory
describes all documented events show in perf list.

The events shown in perf list are the most fine grained events with a single
bit of the event mask set. More general events may be enable by setting
multiple mask bits in config. For example, all Device to Host Read Requests
may be captured on a single counter by setting the bits for all of

* d2h_req_rdcurr
* d2h_req_rdown
* d2h_req_rdshared
* d2h_req_rdany
* d2h_req_rdownnodata

Example of usage::

  $#perf list
  cxl_pmu_mem0.0/clock_ticks/                        [Kernel PMU event]
  cxl_pmu_mem0.0/d2h_req_rdshared/                   [Kernel PMU event]
  cxl_pmu_mem0.0/h2d_req_snpcur/                     [Kernel PMU event]
  cxl_pmu_mem0.0/h2d_req_snpdata/                    [Kernel PMU event]
  cxl_pmu_mem0.0/h2d_req_snpinv/                     [Kernel PMU event]
  -----------------------------------------------------------

  $# perf stat -a -e cxl_pmu_mem0.0/clock_ticks/ -e cxl_pmu_mem0.0/d2h_req_rdshared/

Vendor specific events may also be available and if so can be used via

  $# perf stat -a -e cxl_pmu_mem0.0/vid=VID,gid=GID,mask=MASK/

The driver does not support sampling so "perf record" is unsupported.
It only supports system-wide counting so attaching to a task is
unsupported.
+1 −0
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@@ -21,3 +21,4 @@ Performance monitor support
   alibaba_pmu
   nvidia-pmu
   meson-ddr-pmu
   cxl
+7 −0
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@@ -5203,6 +5203,13 @@ S: Maintained
F:	drivers/cxl/
F:	include/uapi/linux/cxl_mem.h
COMPUTE EXPRESS LINK PMU (CPMU)
M:	Jonathan Cameron <jonathan.cameron@huawei.com>
L:	linux-cxl@vger.kernel.org
S:	Maintained
F:	Documentation/admin-guide/perf/cxl.rst
F:	drivers/perf/cxl_pmu.c
CONEXANT ACCESSRUNNER USB DRIVER
L:	accessrunner-general@lists.sourceforge.net
S:	Orphan
+14 −0
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@@ -82,6 +82,7 @@ config CXL_PMEM
config CXL_MEM
	tristate "CXL: Memory Expansion"
	depends on CXL_PCI
	select FW_UPLOAD
	default CXL_BUS
	help
	  The CXL.mem protocol allows a device to act as a provider of "System
@@ -139,4 +140,17 @@ config CXL_REGION_INVALIDATION_TEST
	  If unsure, or if this kernel is meant for production environments,
	  say N.

config CXL_PMU
	tristate "CXL Performance Monitoring Unit"
	default CXL_BUS
	depends on PERF_EVENTS
	help
	  Support performance monitoring as defined in CXL rev 3.0
	  section 13.2: Performance Monitoring. CXL components may have
	  one or more CXL Performance Monitoring Units (CPMUs).

	  Say 'y/m' to enable a driver that will attach to performance
	  monitoring units and provide standard perf based interfaces.

	  If unsure say 'm'.
endif
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