Commit d20f7a09 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'gpio-updates-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux 

Pull gpio updates from Bartosz Golaszewski:
 "We have a single new driver, new features in others and some cleanups
  all over the place.

  Nothing really stands out and it is all relatively small.

   - new driver: gpio-modepin (plus relevant change in zynqmp firmware)

   - add interrupt support to gpio-virtio

   - enable the 'gpio-line-names' property in the DT bindings for
     gpio-rockchip

   - use the subsystem helpers where applicable in gpio-uniphier instead
     of accessing IRQ structures directly

   - code shrink in gpio-xilinx

   - add interrupt to gpio-mlxbf2 (and include the removal of custom
     interrupt code from the mellanox ethernet driver)

   - support multiple interrupts per bank in gpio-tegra186 (and force
     one interrupt per bank in older models)

   - fix GPIO line IRQ offset calculation in gpio-realtek-otto

   - drop unneeded MODULE_ALIAS expansions in multiple drivers

   - code cleanup in gpio-aggregator

   - minor improvements in gpio-max730x and gpio-mc33880

   - Kconfig cleanups"

* tag 'gpio-updates-for-v5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
  virtio_gpio: drop packed attribute
  gpio: virtio: Add IRQ support
  gpio: realtek-otto: fix GPIO line IRQ offset
  gpio: clean up Kconfig file
  net: mellanox: mlxbf_gige: Replace non-standard interrupt handling
  gpio: mlxbf2: Introduce IRQ support
  gpio: mc33880: Drop if with an always false condition
  gpio: max730x: Make __max730x_remove() return void
  gpio: aggregator: Wrap access to gpiochip_fwd.tmp[]
  gpio: modepin: Add driver support for modepin GPIO controller
  dt-bindings: gpio: zynqmp: Add binding documentation for modepin
  firmware: zynqmp: Add MMIO read and write support for PS_MODE pin
  gpio: tps65218: drop unneeded MODULE_ALIAS
  gpio: max77620: drop unneeded MODULE_ALIAS
  gpio: xilinx: simplify getting .driver_data
  gpio: tegra186: Support multiple interrupts per bank
  gpio: tegra186: Force one interrupt per bank
  gpio: uniphier: Use helper functions to get private data from IRQ data
  gpio: uniphier: Use helper function to get IRQ hardware number
  dt-bindings: gpio: add gpio-line-names to rockchip,gpio-bank.yaml
parents dd72945c 7d0003da

Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml

+2 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ properties: 


  gpio-controller: true



  gpio-line-names: true



  "#gpio-cells":

    const: 2

Documentation/devicetree/bindings/gpio/xlnx,zynqmp-gpio-modepin.yaml

0 → 100644
+43 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: "http://devicetree.org/schemas/gpio/xlnx,zynqmp-gpio-modepin.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: ZynqMP Mode Pin GPIO controller



description:

  PS_MODE is 4-bits boot mode pins sampled on POR deassertion. Mode Pin

  GPIO controller with configurable from numbers of pins (from 0 to 3 per

  PS_MODE). Every pin can be configured as input/output.



maintainers:

  - Piyush Mehta <piyush.mehta@xilinx.com>



properties:

  compatible:

    const: xlnx,zynqmp-gpio-modepin



  gpio-controller: true



  "#gpio-cells":

    const: 2



required:

  - compatible

  - gpio-controller

  - "#gpio-cells"



additionalProperties: false



examples:

  - |

    zynqmp-firmware {

        gpio {

            compatible = "xlnx,zynqmp-gpio-modepin";

            gpio-controller;

            #gpio-cells = <2>;

        };

    };



...

drivers/firmware/xilinx/zynqmp.c

+46 −0
Original line number Diff line number Diff line
@@ -28,6 +28,13 @@ 
/* Max HashMap Order for PM API feature check (1<<7 = 128) */

#define PM_API_FEATURE_CHECK_MAX_ORDER  7



/* CRL registers and bitfields */

#define CRL_APB_BASE			0xFF5E0000U

/* BOOT_PIN_CTRL- Used to control the mode pins after boot */

#define CRL_APB_BOOT_PIN_CTRL		(CRL_APB_BASE + (0x250U))

/* BOOT_PIN_CTRL_MASK- out_val[11:8], out_en[3:0] */

#define CRL_APB_BOOTPIN_CTRL_MASK	0xF0FU



static bool feature_check_enabled;

static DEFINE_HASHTABLE(pm_api_features_map, PM_API_FEATURE_CHECK_MAX_ORDER);
@@ -942,6 +949,45 @@ int zynqmp_pm_pinctrl_set_config(const u32 pin, const u32 param, 
}

EXPORT_SYMBOL_GPL(zynqmp_pm_pinctrl_set_config);



/**

 * zynqmp_pm_bootmode_read() - PM Config API for read bootpin status

 * @ps_mode: Returned output value of ps_mode

 *

 * This API function is to be used for notify the power management controller

 * to read bootpin status.

 *

 * Return: status, either success or error+reason

 */

unsigned int zynqmp_pm_bootmode_read(u32 *ps_mode)

{

	unsigned int ret;

	u32 ret_payload[PAYLOAD_ARG_CNT];



	ret = zynqmp_pm_invoke_fn(PM_MMIO_READ, CRL_APB_BOOT_PIN_CTRL, 0,

				  0, 0, ret_payload);



	*ps_mode = ret_payload[1];



	return ret;

}

EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_read);



/**

 * zynqmp_pm_bootmode_write() - PM Config API for Configure bootpin

 * @ps_mode: Value to be written to the bootpin ctrl register

 *

 * This API function is to be used for notify the power management controller

 * to configure bootpin.

 *

 * Return: Returns status, either success or error+reason

 */

int zynqmp_pm_bootmode_write(u32 ps_mode)

{

	return zynqmp_pm_invoke_fn(PM_MMIO_WRITE, CRL_APB_BOOT_PIN_CTRL,

				   CRL_APB_BOOTPIN_CTRL_MASK, ps_mode, 0, NULL);

}

EXPORT_SYMBOL_GPL(zynqmp_pm_bootmode_write);



/**

 * zynqmp_pm_init_finalize() - PM call to inform firmware that the caller

 *			       master has initialized its own power management

drivers/gpio/Kconfig

+68 −55
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ menuconfig GPIOLIB 
	bool "GPIO Support"

	help

	  This enables GPIO support through the generic GPIO library.

	  You only need to enable this, if you also want to enable

	  You only need to enable this if you also want to enable

	  one or more of the GPIO drivers below.



	  If unsure, say N.
@@ -140,8 +140,8 @@ config GPIO_AMDPT 
	depends on ACPI

	select GPIO_GENERIC

	help

	  driver for GPIO functionality on Promontory IOHub

	  Require ACPI ASL code to enumerate as a platform device.

	  Driver for GPIO functionality on Promontory IOHub.

	  Requires ACPI ASL code to enumerate as a platform device.



config GPIO_ASPEED

	tristate "Aspeed GPIO support"
@@ -306,7 +306,7 @@ config GPIO_HISI 
	help

	  Say Y or M here to build support for the HiSilicon GPIO controller

	  driver GPIO block.

	  This GPIO controller support double-edge interrupt and multi-core

	  This GPIO controller supports double-edge interrupt and multi-core

	  concurrent access.



config GPIO_HLWD
@@ -326,7 +326,7 @@ config GPIO_ICH 
	help

	  Say yes here to support the GPIO functionality of a number of Intel

	  ICH-based chipsets.  Currently supported devices: ICH6, ICH7, ICH8

	  ICH9, ICH10, Series 5/3400 (eg Ibex Peak), Series 6/C200 (eg

	  ICH9, ICH10, Series 5/3400 (e.g. Ibex Peak), Series 6/C200 (e.g.

	  Cougar Point), NM10 (Tiger Point), and 3100 (Whitmore Lake).



	  If unsure, say N.
@@ -337,7 +337,7 @@ config GPIO_IOP 
	select GPIO_GENERIC

	help

	  Say yes here to support the GPIO functionality of a number of Intel

	  IOP32X or IOP33X.

	  IOP32X or IOP33X series of chips.



	  If unsure, say N.
@@ -364,7 +364,7 @@ config GPIO_LOONGSON 
	bool "Loongson-2/3 GPIO support"

	depends on CPU_LOONGSON2EF || CPU_LOONGSON64

	help

	  driver for GPIO functionality on Loongson-2F/3A/3B processors.

	  Driver for GPIO functionality on Loongson-2F/3A/3B processors.



config GPIO_LPC18XX

	tristate "NXP LPC18XX/43XX GPIO support"
@@ -392,15 +392,15 @@ config GPIO_MENZ127 
	depends on MCB

	select GPIO_GENERIC

	help

	  Say yes here to support the MEN 16Z127 GPIO Controller

	  Say yes here to support the MEN 16Z127 GPIO Controller.



config GPIO_MM_LANTIQ

	bool "Lantiq Memory mapped GPIOs"

	depends on LANTIQ && SOC_XWAY

	help

	  This enables support for memory mapped GPIOs on the External Bus Unit

	  (EBU) found on Lantiq SoCs. The gpios are output only as they are

	  created by attaching a 16bit latch to the bus.

	  (EBU) found on Lantiq SoCs. The GPIOs are output only as they are

	  created by attaching a 16-bit latch to the bus.



config GPIO_MPC5200

	def_bool y
@@ -424,7 +424,7 @@ config GPIO_MT7621 
	select GPIO_GENERIC

	select GPIOLIB_IRQCHIP

	help

	  Say yes here to support the Mediatek MT7621 SoC GPIO device

	  Say yes here to support the Mediatek MT7621 SoC GPIO device.



config GPIO_MVEBU

	def_bool y
@@ -469,7 +469,7 @@ config GPIO_PL061 
	select IRQ_DOMAIN

	select GPIOLIB_IRQCHIP

	help

	  Say yes here to support the PrimeCell PL061 GPIO device

	  Say yes here to support the PrimeCell PL061 GPIO device.



config GPIO_PMIC_EIC_SPRD

	tristate "Spreadtrum PMIC EIC support"
@@ -483,7 +483,7 @@ config GPIO_PXA 
	bool "PXA GPIO support"

	depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST

	help

	  Say yes here to support the PXA GPIO device

	  Say yes here to support the PXA GPIO device.



config GPIO_RCAR

	tristate "Renesas R-Car and RZ/G GPIO support"
@@ -573,7 +573,7 @@ config GPIO_SPEAR_SPICS 
	depends on PLAT_SPEAR

	select GENERIC_IRQ_CHIP

	help

	  Say yes here to support ST SPEAr SPI Chip Select as GPIO device

	  Say yes here to support ST SPEAr SPI Chip Select as GPIO device.



config GPIO_SPRD

	tristate "Spreadtrum GPIO support"
@@ -598,8 +598,8 @@ config GPIO_STP_XWAY 
	help

	  This enables support for the Serial To Parallel (STP) unit found on

	  XWAY SoC. The STP allows the SoC to drive a shift registers cascade,

	  that can be up to 24 bit. This peripheral is aimed at driving leds.

	  Some of the gpios/leds can be auto updated by the soc with dsl and

	  that can be up to 24 bits. This peripheral is aimed at driving LEDs.

	  Some of the GPIOs/LEDs can be auto updated by the SoC with DSL and

	  phy status.



config GPIO_SYSCON
@@ -679,10 +679,10 @@ config GPIO_VISCONTI 
	  Say yes here to support GPIO on Tohisba Visconti.



config GPIO_VR41XX

	tristate "NEC VR4100 series General-purpose I/O Uint support"

	tristate "NEC VR4100 series General-purpose I/O Unit support"

	depends on CPU_VR41XX

	help

	  Say yes here to support the NEC VR4100 series General-purpose I/O Uint

	  Say yes here to support the NEC VR4100 series General-purpose I/O Unit.



config GPIO_VX855

	tristate "VIA VX855/VX875 GPIO"
@@ -690,14 +690,14 @@ config GPIO_VX855 
	select MFD_CORE

	select MFD_VX855

	help

	  Support access to the VX855/VX875 GPIO lines through the gpio library.

	  Support access to the VX855/VX875 GPIO lines through the GPIO library.



	  This driver provides common support for accessing the device,

	  additional drivers must be enabled in order to use the

	  This driver provides common support for accessing the device.

	  Additional drivers must be enabled in order to use the

	  functionality of the device.



config GPIO_WCD934X

	tristate "Qualcomm Technologies Inc WCD9340/WCD9341 gpio controller driver"

	tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"

	depends on MFD_WCD934X && OF_GPIO

	help

         This driver is to support GPIO block found on the Qualcomm Technologies
@@ -727,7 +727,7 @@ config GPIO_XILINX 
	select GPIOLIB_IRQCHIP

	depends on OF_GPIO

	help

	  Say yes here to support the Xilinx FPGA GPIO device

	  Say yes here to support the Xilinx FPGA GPIO device.



config GPIO_XLP

	tristate "Netlogic XLP GPIO support"
@@ -748,7 +748,7 @@ config GPIO_XTENSA 
	depends on !SMP

	help

	  Say yes here to support the Xtensa internal GPIO32 IMPWIRE (input)

	  and EXPSTATE (output) ports

	  and EXPSTATE (output) ports.



config GPIO_ZEVIO

	bool "LSI ZEVIO SoC memory mapped GPIOs"
@@ -763,6 +763,18 @@ config GPIO_ZYNQ 
	help

	  Say yes here to support Xilinx Zynq GPIO controller.



config GPIO_ZYNQMP_MODEPIN

	tristate "ZynqMP ps-mode pin GPIO configuration driver"

	depends on ZYNQMP_FIRMWARE

	default ZYNQMP_FIRMWARE

	help

	  Say yes here to support the ZynqMP ps-mode pin GPIO configuration

	  driver.



	  This ps-mode pin GPIO driver is based on GPIO framework. PS_MODE

	  is 4-bits boot mode pins. It sets and gets the status of

	  the ps-mode pin. Every pin can be configured as input/output.



config GPIO_LOONGSON1

	tristate "Loongson1 GPIO support"

	depends on MACH_LOONGSON32
@@ -773,12 +785,12 @@ config GPIO_LOONGSON1 
config GPIO_AMD_FCH

	tristate "GPIO support for AMD Fusion Controller Hub (G-series SOCs)"

	help

	  This option enables driver for GPIO on AMDs Fusion Controller Hub,

	  as found on G-series SOCs (eg. GX-412TC)

	  This option enables driver for GPIO on AMD's Fusion Controller Hub,

	  as found on G-series SOCs (e.g. GX-412TC).



	  Note: This driver doesn't registers itself automatically, as it

	  needs to be provided with platform specific configuration.

	  (See eg. CONFIG_PCENGINES_APU2.)

	  Note: This driver doesn't register itself automatically, as it

	  needs to be provided with platform-specific configuration.

	  (See e.g. CONFIG_PCENGINES_APU2.)



config GPIO_MSC313

	bool "MStar MSC313 GPIO support"
@@ -788,7 +800,7 @@ config GPIO_MSC313 
	select IRQ_DOMAIN_HIERARCHY

	help

	  Say Y here to support the main GPIO block on MStar/SigmaStar

	  ARMv7 based SoCs.

	  ARMv7-based SoCs.



config GPIO_IDT3243X

	tristate "IDT 79RC3243X GPIO support"
@@ -797,7 +809,7 @@ config GPIO_IDT3243X 
	select GPIOLIB_IRQCHIP

	help

	  Select this option to enable GPIO driver for

	  IDT 79RC3243X based devices like Mikrotik RB532.

	  IDT 79RC3243X-based devices like Mikrotik RB532.



	  To compile this driver as a module, choose M here: the module will

	  be called gpio-idt3243x.
@@ -875,7 +887,7 @@ config GPIO_IT87 
	  well.



	  To compile this driver as a module, choose M here: the module will

	  be called gpio_it87

	  be called gpio_it87.



config GPIO_SCH

	tristate "Intel SCH/TunnelCreek/Centerton/Quark X1000 GPIO"
@@ -891,7 +903,7 @@ config GPIO_SCH 
	  powered by the core power rail and are turned off during sleep

	  modes (S3 and higher). The remaining four GPIOs are powered by

	  the Intel SCH suspend power supply. These GPIOs remain

	  active during S3. The suspend powered GPIOs can be used to wake the

	  active during S3. The suspend-powered GPIOs can be used to wake the

	  system from the Suspend-to-RAM state.



	  The Intel Tunnel Creek processor has 5 GPIOs powered by the
@@ -1044,7 +1056,7 @@ config GPIO_PCA953X_IRQ 
	select GPIOLIB_IRQCHIP

	help

	  Say yes here to enable the pca953x to be used as an interrupt

	  controller. It requires the driver to be built in the kernel.

	  controller.



config GPIO_PCA9570

	tristate "PCA9570 4-Bit I2C GPO expander"
@@ -1171,7 +1183,7 @@ config GPIO_CRYSTAL_COVE 
	help

	  Support for GPIO pins on Crystal Cove PMIC.



	  Say Yes if you have a Intel SoC based tablet with Crystal Cove PMIC

	  Say Yes if you have a Intel SoC-based tablet with Crystal Cove PMIC

	  inside.



	  This driver can also be built as a module. If so, the module will be
@@ -1201,7 +1213,7 @@ config GPIO_DA9055 
	  Say yes here to enable the GPIO driver for the DA9055 chip.



	  The Dialog DA9055 PMIC chip has 3 GPIO pins that can be

	  be controller by this driver.

	  be controlled by this driver.



	  If driver is built as a module it will be called gpio-da9055.
@@ -1223,7 +1235,7 @@ config HTC_EGPIO 
	help

	  This driver supports the CPLD egpio chip present on

	  several HTC phones.  It provides basic support for input

	  pins, output pins, and irqs.

	  pins, output pins, and IRQs.



config GPIO_JANZ_TTL

	tristate "Janz VMOD-TTL Digital IO Module"
@@ -1284,8 +1296,8 @@ config GPIO_MAX77620 
	help

	  GPIO driver for MAX77620 and MAX20024 PMIC from Maxim Semiconductor.

	  MAX77620 PMIC has 8 pins that can be configured as GPIOs. The

	  driver also provides interrupt support for each of the gpios.

	  Say yes here to enable the max77620 to be used as gpio controller.

	  driver also provides interrupt support for each of the GPIOs.

	  Say yes here to enable the max77620 to be used as GPIO controller.



config GPIO_MAX77650

	tristate "Maxim MAX77650/77651 GPIO support"
@@ -1307,8 +1319,8 @@ config GPIO_RC5T583 
	help

	  Select this option to enable GPIO driver for the Ricoh RC5T583

	  chip family.

	  This driver provides the support for driving/reading the gpio pins

	  of RC5T583 device through standard gpio library.

	  This driver provides the support for driving/reading the GPIO pins

	  of RC5T583 device through standard GPIO library.



config GPIO_SL28CPLD

	tristate "Kontron sl28cpld GPIO support"
@@ -1377,7 +1389,7 @@ config GPIO_TPS65912 
	tristate "TI TPS65912 GPIO"

	depends on MFD_TPS65912

	help

	  This driver supports TPS65912 gpio chip

	  This driver supports TPS65912 GPIO chip.



config GPIO_TPS68470

	bool "TPS68470 GPIO"
@@ -1385,7 +1397,7 @@ config GPIO_TPS68470 
	help

	  Select this option to enable GPIO driver for the TPS68470

	  chip family.

	  There are 7 GPIOs and few sensor related GPIOs supported

	  There are 7 GPIOs and few sensor-related GPIOs supported

	  by the TPS68470. While the 7 GPIOs can be configured as

	  input or output as appropriate, the sensor related GPIOs

	  are "output only" GPIOs.
@@ -1430,7 +1442,7 @@ config GPIO_WHISKEY_COVE 
	help

	  Support for GPIO pins on Whiskey Cove PMIC.



	  Say Yes if you have a Intel SoC based tablet with Whiskey Cove PMIC

	  Say Yes if you have an Intel SoC-based tablet with Whiskey Cove PMIC

	  inside.



	  This driver can also be built as a module. If so, the module will be
@@ -1469,8 +1481,8 @@ config GPIO_AMD8111 
	help

	  The AMD 8111 southbridge contains 32 GPIO pins which can be used.



	  Note, that usually system firmware/ACPI handles GPIO pins on their

	  own and users might easily break their systems with uncarefull usage

	  Note that usually system firmware/ACPI handles GPIO pins on their

	  own and users might easily break their systems with uncareful usage

	  of this driver!



	  If unsure, say N
@@ -1527,7 +1539,7 @@ config GPIO_PCH 
	depends on X86_32 || MIPS || COMPILE_TEST

	select GENERIC_IRQ_CHIP

	help

	  This driver is for PCH(Platform controller Hub) GPIO of Intel Topcliff

	  This driver is for PCH (Platform Controller Hub) GPIO of Intel Topcliff,

	  which is an IOH (Input/Output Hub) for x86 embedded processor.

	  This driver can access PCH GPIO device.
@@ -1584,7 +1596,7 @@ config GPIO_74X164 
	help

	  Driver for 74x164 compatible serial-in/parallel-out 8-outputs

	  shift registers. This driver can be used to provide access

	  to more gpio outputs.

	  to more GPIO outputs.



config GPIO_MAX3191X

	tristate "Maxim MAX3191x industrial serializer"
@@ -1674,6 +1686,7 @@ config GPIO_MOCKUP 
config GPIO_VIRTIO

	tristate "VirtIO GPIO support"

	depends on VIRTIO

	select GPIOLIB_IRQCHIP

	help

	  Say Y here to enable guest support for virtio-based GPIO controllers.

drivers/gpio/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -184,3 +184,4 @@ obj-$(CONFIG_GPIO_XRA1403) += gpio-xra1403.o 
obj-$(CONFIG_GPIO_XTENSA)		+= gpio-xtensa.o

obj-$(CONFIG_GPIO_ZEVIO)		+= gpio-zevio.o

obj-$(CONFIG_GPIO_ZYNQ)			+= gpio-zynq.o

obj-$(CONFIG_GPIO_ZYNQMP_MODEPIN)	+= gpio-zynqmp-modepin.o