Commit d2063080 authored by Lyude Paul's avatar Lyude Paul
Browse files

drm/i915/gen9_bc: Introduce TGP PCH DDC pin mappings 



With the introduction of gen9_bc, where Intel combines Cometlake CPUs with
a Tigerpoint PCH, we'll need to introduce new DDC pin mappings for this
platform in order to make all of the display connectors work. So, let's do
that.

Changes since v4:
* Split this into it's own patch - vsyrjala
Changes since v5:
* Rename gen9bc_port_to_ddc_pin() to gen9bc_tgp_port_to_ddc_pin()

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
[originally from Tejas's work]
Signed-off-by: default avatarTejas Upadhyay <tejaskumarx.surendrakumar.upadhyay@intel.com>
Signed-off-by: default avatarLyude Paul <lyude@redhat.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210209212832.1401815-3-lyude@redhat.com
parent 4b97039e

drivers/gpu/drm/i915/display/intel_bios.c

+9 −0
Original line number Diff line number Diff line
@@ -1638,6 +1638,12 @@ static const u8 adls_ddc_pin_map[] = { 
	[ADLS_DDC_BUS_PORT_TC4] = GMBUS_PIN_12_TC4_ICP,

};



static const u8 gen9bc_tgp_ddc_pin_map[] = {

	[DDC_BUS_DDI_B] = GMBUS_PIN_2_BXT,

	[DDC_BUS_DDI_C] = GMBUS_PIN_9_TC1_ICP,

	[DDC_BUS_DDI_D] = GMBUS_PIN_10_TC2_ICP,

};



static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin)

{

	const u8 *ddc_pin_map;
@@ -1651,6 +1657,9 @@ static u8 map_ddc_pin(struct drm_i915_private *dev_priv, u8 vbt_pin) 
	} else if (IS_ROCKETLAKE(dev_priv) && INTEL_PCH_TYPE(dev_priv) == PCH_TGP) {

		ddc_pin_map = rkl_pch_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);

	} else if (HAS_PCH_TGP(dev_priv) && IS_GEN9_BC(dev_priv)) {

		ddc_pin_map = gen9bc_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(gen9bc_tgp_ddc_pin_map);

	} else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {

		ddc_pin_map = icp_ddc_pin_map;

		n_entries = ARRAY_SIZE(icp_ddc_pin_map);

drivers/gpu/drm/i915/display/intel_hdmi.c

+20 −0
Original line number Diff line number Diff line
@@ -3138,6 +3138,24 @@ static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) 
	return GMBUS_PIN_1_BXT + phy;

}



static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)

{

	enum phy phy = intel_port_to_phy(i915, port);



	drm_WARN_ON(&i915->drm, port == PORT_A);



	/*

	 * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,

	 * final two outputs use type-c pins, even though they're actually

	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for

	 * all outputs.

	 */

	if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)

		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;



	return GMBUS_PIN_1_BXT + phy;

}



static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)

{

	return intel_port_to_phy(dev_priv, port) + 1;
@@ -3202,6 +3220,8 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder) 
		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);

	else if (IS_ROCKETLAKE(dev_priv))

		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);

	else if (IS_GEN9_BC(dev_priv) && HAS_PCH_TGP(dev_priv))

		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);

	else if (HAS_PCH_MCC(dev_priv))

		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);

	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)