Commit d19afe7b authored by Mauro Carvalho Chehab's avatar Mauro Carvalho Chehab Committed by Bjorn Helgaas
Browse files

PCI: kirin: Use regmap for APB registers 

The PHY layer need to access APB registers too, for Kirin 970.  So place
them into a named regmap.

Link: https://lore.kernel.org/r/daf0e4bda5a69a5ac8484e70f09351a959805c8c.1634812676.git.mchehab+huawei@kernel.org


Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Acked-by: default avatarXiaowei Song <songxiaowei@hisilicon.com>
parent 000f60db

drivers/pci/controller/dwc/pcie-kirin.c

+26 −23
Original line number Diff line number Diff line
@@ -61,8 +61,8 @@ struct kirin_pcie { 
	enum pcie_kirin_phy_type	type;



	struct dw_pcie	*pci;

	struct regmap   *apb;

	struct phy	*phy;

	void __iomem	*apb_base;

	void		*phy_priv;	/* only for PCIE_KIRIN_INTERNAL_PHY */

};
@@ -340,25 +340,27 @@ static int hi3660_pcie_phy_init(struct platform_device *pdev, 
 * The non-PHY part starts here

 */



/* Registers in PCIeCTRL */

static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,

					 u32 val, u32 reg)

{

	writel(val, kirin_pcie->apb_base + reg);

}



static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)

{

	return readl(kirin_pcie->apb_base + reg);

}

static const struct regmap_config pcie_kirin_regmap_conf = {

	.name = "kirin_pcie_apb",

	.reg_bits = 32,

	.val_bits = 32,

	.reg_stride = 4,

};



static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,

				    struct platform_device *pdev)

{

	kirin_pcie->apb_base =

		devm_platform_ioremap_resource_byname(pdev, "apb");

	if (IS_ERR(kirin_pcie->apb_base))

		return PTR_ERR(kirin_pcie->apb_base);

	struct device *dev = &pdev->dev;

	void __iomem *apb_base;



	apb_base = devm_platform_ioremap_resource_byname(pdev, "apb");

	if (IS_ERR(apb_base))

		return PTR_ERR(apb_base);



	kirin_pcie->apb = devm_regmap_init_mmio(dev, apb_base,

						&pcie_kirin_regmap_conf);

	if (IS_ERR(kirin_pcie->apb))

		return PTR_ERR(kirin_pcie->apb);



	return 0;

}
@@ -368,13 +370,13 @@ static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie, 
{

	u32 val;



	val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL0_ADDR);

	regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, &val);

	if (on)

		val = val | PCIE_ELBI_SLV_DBI_ENABLE;

	else

		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;



	kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL0_ADDR);

	regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL0_ADDR, val);

}



static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie,
@@ -382,13 +384,13 @@ static void kirin_pcie_sideband_dbi_r_mode(struct kirin_pcie *kirin_pcie, 
{

	u32 val;



	val = kirin_apb_ctrl_readl(kirin_pcie, SOC_PCIECTRL_CTRL1_ADDR);

	regmap_read(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, &val);

	if (on)

		val = val | PCIE_ELBI_SLV_DBI_ENABLE;

	else

		val = val & ~PCIE_ELBI_SLV_DBI_ENABLE;



	kirin_apb_ctrl_writel(kirin_pcie, val, SOC_PCIECTRL_CTRL1_ADDR);

	regmap_write(kirin_pcie->apb, SOC_PCIECTRL_CTRL1_ADDR, val);

}



static int kirin_pcie_rd_own_conf(struct pci_bus *bus, unsigned int devfn,
@@ -448,8 +450,9 @@ static void kirin_pcie_write_dbi(struct dw_pcie *pci, void __iomem *base, 
static int kirin_pcie_link_up(struct dw_pcie *pci)

{

	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);

	u32 val = kirin_apb_ctrl_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);

	u32 val;



	regmap_read(kirin_pcie->apb, PCIE_APB_PHY_STATUS0, &val);

	if ((val & PCIE_LINKUP_ENABLE) == PCIE_LINKUP_ENABLE)

		return 1;
@@ -461,8 +464,8 @@ static int kirin_pcie_start_link(struct dw_pcie *pci) 
	struct kirin_pcie *kirin_pcie = to_kirin_pcie(pci);



	/* assert LTSSM enable */

	kirin_apb_ctrl_writel(kirin_pcie, PCIE_LTSSM_ENABLE_BIT,

			      PCIE_APP_LTSSM_ENABLE);

	regmap_write(kirin_pcie->apb, PCIE_APP_LTSSM_ENABLE,

		     PCIE_LTSSM_ENABLE_BIT);



	return 0;

}