Commit d1489208 authored by Hariprasad Kelam's avatar Hariprasad Kelam Committed by David S. Miller
Browse files

octeontx2-af: cn10k: RPM hardware timestamp configuration 



MAC on CN10K support hardware timestamping such that 8 bytes addition
header is prepended to incoming packets. This patch does necessary
configuration to enable Hardware time stamping upon receiving request
from PF netdev interfaces.

Timestamp configuration is different on MAC (CGX) Octeontx2 silicon
and MAC (RPM) OcteonTX3 CN10k. Based on silicon variant appropriate
fn() pointer is called. Refactor MAC specific mbox messages to remove
unnecessary gaps in mboxids.

Signed-off-by: default avatarHariprasad Kelam <hkelam@marvell.com>
Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e37e08ff

drivers/net/ethernet/marvell/octeontx2/af/cgx.c

+5 −5
Original line number Diff line number Diff line
@@ -838,9 +838,6 @@ void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable) 
	if (!cgx)

		return;



	if (is_dev_rpm(cgx))

		return;



	if (enable) {

		/* Enable inbound PTP timestamping */

		cfg = cgx_read(cgx, lmac_id, CGXX_GMP_GMI_RXX_FRM_CTL);
@@ -1545,9 +1542,11 @@ static int cgx_lmac_exit(struct cgx *cgx) 
static void cgx_populate_features(struct cgx *cgx)

{

	if (is_dev_rpm(cgx))

		cgx->hw_features =  (RVU_MAC_RPM | RVU_LMAC_FEAT_FC);

		cgx->hw_features = (RVU_LMAC_FEAT_DMACF | RVU_MAC_RPM |

				    RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);

	else

		cgx->hw_features = (RVU_LMAC_FEAT_FC | RVU_LMAC_FEAT_PTP);

		cgx->hw_features = (RVU_LMAC_FEAT_FC  | RVU_LMAC_FEAT_HIGIG2 |

				    RVU_LMAC_FEAT_PTP | RVU_LMAC_FEAT_DMACF);

}



static struct mac_ops	cgx_mac_ops    = {
@@ -1571,6 +1570,7 @@ static struct mac_ops cgx_mac_ops = { 
	.mac_get_pause_frm_status =	cgx_lmac_get_pause_frm_status,

	.mac_enadis_pause_frm =		cgx_lmac_enadis_pause_frm,

	.mac_pause_frm_config =		cgx_lmac_pause_frm_config,

	.mac_enadis_ptp_config =	cgx_lmac_ptp_config,

};



static int cgx_probe(struct pci_dev *pdev, const struct pci_device_id *id)

drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h

+5 −0
Original line number Diff line number Diff line
@@ -102,6 +102,11 @@ struct mac_ops { 
	void			(*mac_pause_frm_config)(void  *cgxd,

							int lmac_id,

							bool enable);



	/* Enable/Disable Inbound PTP */

	void			(*mac_enadis_ptp_config)(void  *cgxd,

							 int lmac_id,

							 bool enable);

};



struct cgx {

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+22 −19
Original line number Diff line number Diff line
@@ -154,23 +154,23 @@ M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \ 
M(CGX_PTP_RX_DISABLE,	0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)	\

M(CGX_CFG_PAUSE_FRM,	0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,	\

			       cgx_pause_frm_cfg)			\

M(CGX_FW_DATA_GET,	0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \

M(CGX_FEC_SET,		0x210, cgx_set_fec_param, fec_mode, fec_mode) \

M(CGX_FEC_STATS,	0x211, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \

M(CGX_GET_PHY_FEC_STATS, 0x212, cgx_get_phy_fec_stats, msg_req, msg_rsp) \

M(CGX_FW_DATA_GET,	0x213, cgx_get_aux_link_info, msg_req, cgx_fw_data) \

M(CGX_SET_LINK_MODE,	0x214, cgx_set_link_mode, cgx_set_link_mode_req,\

			       cgx_set_link_mode_rsp)	\

M(CGX_FEATURES_GET,	0x215, cgx_features_get, msg_req,		\

			       cgx_features_info_msg)			\

M(RPM_STATS,		0x216, rpm_stats, msg_req, rpm_stats_rsp)	\

M(CGX_MAC_ADDR_ADD,	0x217, cgx_mac_addr_add, cgx_mac_addr_add_req,    \

M(CGX_MAC_ADDR_ADD,	0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,    \

				cgx_mac_addr_add_rsp)		\

M(CGX_MAC_ADDR_DEL,	0x218, cgx_mac_addr_del, cgx_mac_addr_del_req,    \

M(CGX_MAC_ADDR_DEL,	0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,    \

			       msg_rsp)		\

M(CGX_MAC_MAX_ENTRIES_GET, 0x219, cgx_mac_max_entries_get, msg_req,    \

M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,    \

				  cgx_max_dmac_entries_get_rsp)		\

M(CGX_MAC_ADDR_RESET,	0x21A, cgx_mac_addr_reset, msg_req, msg_rsp)	\

M(CGX_MAC_ADDR_UPDATE,	0x21B, cgx_mac_addr_update, cgx_mac_addr_update_req, \

M(CGX_FEC_STATS,	0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \

M(CGX_SET_LINK_MODE,	0x218, cgx_set_link_mode, cgx_set_link_mode_req,\

			       cgx_set_link_mode_rsp)	\

M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \

M(CGX_FEATURES_GET,	0x21B, cgx_features_get, msg_req,		\

			       cgx_features_info_msg)			\

M(RPM_STATS,		0x21C, rpm_stats, msg_req, rpm_stats_rsp)	\

M(CGX_MAC_ADDR_RESET,	0x21D, cgx_mac_addr_reset, msg_req, msg_rsp)	\

M(CGX_MAC_ADDR_UPDATE,	0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \

			       msg_rsp)					\

/* NPA mbox IDs (range 0x400 - 0x5FF) */				\

M(NPA_LF_ALLOC,		0x400, npa_lf_alloc,				\
@@ -583,10 +583,13 @@ struct cgx_mac_addr_update_req { 
};



#define RVU_LMAC_FEAT_FC		BIT_ULL(0) /* pause frames */

#define RVU_LMAC_FEAT_PTP		BIT_ULL(1) /* precision time protocol */

#define RVU_MAC_VERSION			BIT_ULL(2)

#define RVU_MAC_CGX			BIT_ULL(3)

#define RVU_MAC_RPM			BIT_ULL(4)

#define	RVU_LMAC_FEAT_HIGIG2		BIT_ULL(1)

			/* flow control from physical link higig2 messages */

#define RVU_LMAC_FEAT_PTP		BIT_ULL(2) /* precison time protocol */

#define RVU_LMAC_FEAT_DMACF		BIT_ULL(3) /* DMAC FILTER */

#define RVU_MAC_VERSION			BIT_ULL(4)

#define RVU_MAC_CGX			BIT_ULL(5)

#define RVU_MAC_RPM			BIT_ULL(6)



struct cgx_features_info_msg {

	struct mbox_msghdr hdr;

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

+17 −0
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ static struct mac_ops rpm_mac_ops = { 
	.mac_get_pause_frm_status =	rpm_lmac_get_pause_frm_status,

	.mac_enadis_pause_frm =		rpm_lmac_enadis_pause_frm,

	.mac_pause_frm_config =		rpm_lmac_pause_frm_config,

	.mac_enadis_ptp_config =	rpm_lmac_ptp_config,

};



struct mac_ops *rpm_get_mac_ops(void)
@@ -270,3 +271,19 @@ int rpm_lmac_internal_loopback(void *rpmd, int lmac_id, bool enable) 


	return 0;

}



void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable)

{

	rpm_t *rpm = rpmd;

	u64 cfg;



	if (!is_lmac_valid(rpm, lmac_id))

		return;



	cfg = rpm_read(rpm, lmac_id, RPMX_CMRX_CFG);

	if (enable)

		cfg |= RPMX_RX_TS_PREPEND;

	else

		cfg &= ~RPMX_RX_TS_PREPEND;

	rpm_write(rpm, lmac_id, RPMX_CMRX_CFG, cfg);

}

drivers/net/ethernet/marvell/octeontx2/af/rpm.h

+3 −0
Original line number Diff line number Diff line
@@ -14,6 +14,8 @@ 
#define PCI_DEVID_CN10K_RPM		0xA060



/* Registers */

#define RPMX_CMRX_CFG			0x00

#define RPMX_RX_TS_PREPEND              BIT_ULL(22)

#define RPMX_CMRX_SW_INT                0x180

#define RPMX_CMRX_SW_INT_W1S            0x188

#define RPMX_CMRX_SW_INT_ENA_W1S        0x198
@@ -54,4 +56,5 @@ int rpm_lmac_enadis_pause_frm(void *rpmd, int lmac_id, u8 tx_pause, 
			      u8 rx_pause);

int rpm_get_tx_stats(void *rpmd, int lmac_id, int idx, u64 *tx_stat);

int rpm_get_rx_stats(void *rpmd, int lmac_id, int idx, u64 *rx_stat);

void rpm_lmac_ptp_config(void *rpmd, int lmac_id, bool enable);

#endif /* RPM_H */