Commit d1055173 authored by Like Xu's avatar Like Xu Committed by Paolo Bonzini
Browse files

KVM: x86: Set PEBS_UNAVAIL in IA32_MISC_ENABLE when PEBS is enabled 



The bit 12 represents "Processor Event Based Sampling Unavailable (RO)" :
	1 = PEBS is not supported.
	0 = PEBS is supported.

A write to this PEBS_UNAVL available bit will bring #GP(0) when guest PEBS
is enabled. Some PEBS drivers in guest may care about this bit.

Signed-off-by: default avatarLike Xu <like.xu@linux.intel.com>
Message-Id: <20220411101946.20262-13-likexu@tencent.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 902caeb6

arch/x86/kvm/vmx/pmu_intel.c

+2 −0
Original line number Diff line number Diff line
@@ -605,6 +605,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 
		bitmap_set(pmu->all_valid_pmc_idx, INTEL_PMC_IDX_FIXED_VLBR, 1);



	if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_FORMAT) {

		vcpu->arch.ia32_misc_enable_msr &= ~MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;

		if (vcpu->arch.perf_capabilities & PERF_CAP_PEBS_BASELINE) {

			pmu->pebs_enable_mask = ~pmu->global_ctrl;

			pmu->reserved_bits &= ~ICL_EVENTSEL_ADAPTIVE;
@@ -618,6 +619,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 
				~((1ull << pmu->nr_arch_gp_counters) - 1);

		}

	} else {

		vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;

		vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK;

	}

}

arch/x86/kvm/x86.c

+7 −1
Original line number Diff line number Diff line
@@ -3561,7 +3561,13 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		break;

	case MSR_IA32_MISC_ENABLE: {

		u64 old_val = vcpu->arch.ia32_misc_enable_msr;

		u64 pmu_mask = MSR_IA32_MISC_ENABLE_EMON;

		u64 pmu_mask = MSR_IA32_MISC_ENABLE_EMON |

			MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;



		/* RO bits */

		if (!msr_info->host_initiated &&

		    ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))

			return 1;



		/*

		 * For a dummy user space, the order of setting vPMU capabilities and