Commit d0a4564b authored by Olivier Moysan's avatar Olivier Moysan Committed by Thierry Reding
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pwm: stm32: Enforce settings for PWM capture 



The PWM capture assumes that the input selector is set to default
input and that the slave mode is disabled. Force reset state for
TISEL and SMCR registers to match this requirement.

Note that slave mode disabling is not a pre-requisite by itself
for capture mode, as hardware supports it for PWM capture.
However, the current implementation of the driver does not
allow slave mode for PWM capture. Setting slave mode for PWM
capture results in wrong capture values.

Signed-off-by: default avatarOlivier Moysan <olivier.moysan@foss.st.com>
Acked-by: default avatarLee Jones <lee@kernel.org>
Acked-by: default avatarUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: default avatarThierry Reding <thierry.reding@gmail.com>
parent de614ac3

drivers/pwm/pwm-stm32.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -207,6 +207,10 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, 
	regmap_write(priv->regmap, TIM_ARR, priv->max_arr);

	regmap_write(priv->regmap, TIM_ARR, priv->max_arr);

	regmap_write(priv->regmap, TIM_PSC, psc);

	regmap_write(priv->regmap, TIM_PSC, psc);





	/* Reset input selector to its default input and disable slave mode */

	regmap_write(priv->regmap, TIM_TISEL, 0x0);

	regmap_write(priv->regmap, TIM_SMCR, 0x0);



	/* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */

	/* Map TI1 or TI2 PWM input to IC1 & IC2 (or TI3/4 to IC3 & IC4) */

	regmap_update_bits(priv->regmap,

	regmap_update_bits(priv->regmap,

			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,

			   pwm->hwpwm < 2 ? TIM_CCMR1 : TIM_CCMR2,

include/linux/mfd/stm32-timers.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define TIM_BDTR	0x44	/* Break and Dead-Time Reg */

#define TIM_BDTR	0x44	/* Break and Dead-Time Reg */

#define TIM_DCR		0x48	/* DMA control register    */

#define TIM_DCR		0x48	/* DMA control register    */

#define TIM_DMAR	0x4C	/* DMA register for transfer */

#define TIM_DMAR	0x4C	/* DMA register for transfer */

#define TIM_TISEL	0x68	/* Input Selection         */





#define TIM_CR1_CEN	BIT(0)	/* Counter Enable	   */

#define TIM_CR1_CEN	BIT(0)	/* Counter Enable	   */

#define TIM_CR1_DIR	BIT(4)  /* Counter Direction	   */

#define TIM_CR1_DIR	BIT(4)  /* Counter Direction	   */