Commit d083c232 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Clean up PIPEMISC register defines 



Use REG_BIT() & co. for PIPEMISC* bits, and while at it
fill in the missing dithering bits since we already had some
of them defined.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211112193813.8224-3-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 96e4c3c0

drivers/gpu/drm/i915/display/intel_display.c

+9 −9
Original line number Original line Diff line number Diff line
@@ -3764,18 +3764,18 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 




	switch (crtc_state->pipe_bpp) {

	switch (crtc_state->pipe_bpp) {

	case 18:

	case 18:

		val |= PIPEMISC_6_BPC;

		val |= PIPEMISC_BPC_6;

		break;

		break;

	case 24:

	case 24:

		val |= PIPEMISC_8_BPC;

		val |= PIPEMISC_BPC_8;

		break;

		break;

	case 30:

	case 30:

		val |= PIPEMISC_10_BPC;

		val |= PIPEMISC_BPC_10;

		break;

		break;

	case 36:

	case 36:

		/* Port output 12BPC defined for ADLP+ */

		/* Port output 12BPC defined for ADLP+ */

		if (DISPLAY_VER(dev_priv) > 12)

		if (DISPLAY_VER(dev_priv) > 12)

			val |= PIPEMISC_12_BPC_ADLP;

			val |= PIPEMISC_BPC_12_ADLP;

		break;

		break;

	default:

	default:

		MISSING_CASE(crtc_state->pipe_bpp);

		MISSING_CASE(crtc_state->pipe_bpp);
@@ -3811,7 +3811,7 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state) 
		}

		}





		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),

		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),

			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,

			     PIPE_MISC2_BUBBLE_COUNTER_MASK,

			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :

			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :

			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);

			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);

	}

	}
@@ -3827,11 +3827,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 
	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));

	tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));





	switch (tmp & PIPEMISC_BPC_MASK) {

	switch (tmp & PIPEMISC_BPC_MASK) {

	case PIPEMISC_6_BPC:

	case PIPEMISC_BPC_6:

		return 18;

		return 18;

	case PIPEMISC_8_BPC:

	case PIPEMISC_BPC_8:

		return 24;

		return 24;

	case PIPEMISC_10_BPC:

	case PIPEMISC_BPC_10:

		return 30;

		return 30;

	/*

	/*

	 * PORT OUTPUT 12 BPC defined for ADLP+.

	 * PORT OUTPUT 12 BPC defined for ADLP+.
@@ -3843,7 +3843,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc) 
	 * on older platforms, need to find a workaround for 12 BPC

	 * on older platforms, need to find a workaround for 12 BPC

	 * MIPI DSI HW readout.

	 * MIPI DSI HW readout.

	 */

	 */

	case PIPEMISC_12_BPC_ADLP:

	case PIPEMISC_BPC_12_ADLP:

		if (DISPLAY_VER(dev_priv) > 12)

		if (DISPLAY_VER(dev_priv) > 12)

			return 36;

			return 36;

		fallthrough;

		fallthrough;

drivers/gpu/drm/i915/i915_reg.h

+19 −16
Original line number Original line Diff line number Diff line
@@ -5308,10 +5308,10 @@ enum { 




#define _PIPE_MISC_A			0x70030

#define _PIPE_MISC_A			0x70030

#define _PIPE_MISC_B			0x71030

#define _PIPE_MISC_B			0x71030

#define   PIPEMISC_YUV420_ENABLE	(1 << 27) /* glk+ */

#define   PIPEMISC_YUV420_ENABLE		REG_BIT(27) /* glk+ */

#define   PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */

#define   PIPEMISC_YUV420_MODE_FULL_BLEND	REG_BIT(26) /* glk+ */

#define   PIPEMISC_HDR_MODE_PRECISION	(1 << 23) /* icl+ */

#define   PIPEMISC_HDR_MODE_PRECISION		REG_BIT(23) /* icl+ */

#define   PIPEMISC_OUTPUT_COLORSPACE_YUV  (1 << 11)

#define   PIPEMISC_OUTPUT_COLORSPACE_YUV	REG_BIT(11)

#define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */

#define   PIPEMISC_PIXEL_ROUNDING_TRUNC		REG_BIT(8) /* tgl+ */

/*

/*

 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with

 * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
@@ -5319,21 +5319,24 @@ enum { 
 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:

 * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:

 * 6, 8, 10, 12 BPC.

 * 6, 8, 10, 12 BPC.

 */

 */

#define   PIPEMISC_BPC_MASK		(7 << 5)

#define   PIPEMISC_BPC_MASK			REG_GENMASK(7, 5)

#define   PIPEMISC_8_BPC		(0 << 5)

#define   PIPEMISC_BPC_8			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)

#define   PIPEMISC_10_BPC		(1 << 5)

#define   PIPEMISC_BPC_10			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)

#define   PIPEMISC_6_BPC		(2 << 5)

#define   PIPEMISC_BPC_6			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)

#define   PIPEMISC_12_BPC_ADLP		(4 << 5) /* adlp+ */

#define   PIPEMISC_BPC_12_ADLP			REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */

#define   PIPEMISC_DITHER_ENABLE	(1 << 4)

#define   PIPEMISC_DITHER_ENABLE		REG_BIT(4)

#define   PIPEMISC_DITHER_TYPE_MASK	(3 << 2)

#define   PIPEMISC_DITHER_TYPE_MASK		REG_GENMASK(3, 2)

#define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)

#define   PIPEMISC_DITHER_TYPE_SP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 0)

#define   PIPEMISC_DITHER_TYPE_ST1		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 1)

#define   PIPEMISC_DITHER_TYPE_ST2		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 2)

#define   PIPEMISC_DITHER_TYPE_TEMP		REG_FIELD_PREP(PIPEMISC_DITHER_TYPE_MASK, 3)

#define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)

#define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)





#define _PIPE_MISC2_A					0x7002C

#define _PIPE_MISC2_A					0x7002C

#define _PIPE_MISC2_B					0x7102C

#define _PIPE_MISC2_B					0x7102C

#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)

#define   PIPE_MISC2_BUBBLE_COUNTER_MASK	REG_GENMASK(31, 24)

#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)

#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 80)

#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)

#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS	REG_FIELD_PREP(PIPE_MISC2_BUBBLE_COUNTER_MASK, 20)

#define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)

#define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)





/* Skylake+ pipe bottom (background) color */

/* Skylake+ pipe bottom (background) color */