Commit d0629cea authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: fix wrong register access 



[why]
fw version check was for release branch.
for staging, it has a chance to enter wrong code path.

Reviewed-by: default avatarHansen Dsouza <hansen.dsouza@amd.com>
Acked-by: default avatarBrian Chang <Brian.Chang@amd.com>
Signed-off-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 595091c6

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link_encoder.c

+3 −0
Original line number Diff line number Diff line
@@ -104,6 +104,9 @@ static bool has_query_dp_alt(struct link_encoder *enc) 
{

	struct dc_dmub_srv *dc_dmub_srv = enc->ctx->dmub_srv;



	if (enc->ctx->dce_version >= DCN_VERSION_3_15)

		return true;



	/* Supports development firmware and firmware >= 4.0.11 */

	return dc_dmub_srv &&

	       !(dc_dmub_srv->dmub->fw_version >= DMUB_FW_VERSION(4, 0, 0) &&

drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dio_stream_encoder.c

+1 −0
Original line number Diff line number Diff line
@@ -317,6 +317,7 @@ static void enc314_stream_encoder_dp_unblank( 
	/* switch DP encoder to CRTC data, but reset it the fifo first. It may happen

	 * that it overflows during mode transition, and sometimes doesn't recover.

	 */

	REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_READ_START_LEVEL, 0x7);

	REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 1);

	udelay(10);