Commit d044a9fb authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Convert ID_DFR0_EL1 to automatic generation 



Convert ID_DFR0_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221130171637.718182-38-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 58e01051

arch/arm64/include/asm/sysreg.h

+0 −14
Original line number Diff line number Diff line
@@ -165,7 +165,6 @@ 
#define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)

#define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)



#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)

#define SYS_ID_DFR1_EL1			sys_reg(3, 0, 0, 3, 5)



#define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
@@ -670,21 +669,8 @@ 
#define ID_AA64MMFR0_EL1_PARANGE_MAX	ID_AA64MMFR0_EL1_PARANGE_48

#endif



#define ID_DFR0_EL1_PerfMon_PMUv3		0x3

#define ID_DFR0_EL1_PerfMon_PMUv3p1		0x4

#define ID_DFR0_EL1_PerfMon_PMUv3p4		0x5

#define ID_DFR0_EL1_PerfMon_PMUv3p5		0x6



#define ID_DFR1_EL1_MTPMU_SHIFT		0



#define ID_DFR0_EL1_PerfMon_SHIFT	24

#define ID_DFR0_EL1_MProfDbg_SHIFT	20

#define ID_DFR0_EL1_MMapTrc_SHIFT	16

#define ID_DFR0_EL1_CopTrc_SHIFT	12

#define ID_DFR0_EL1_MMapDbg_SHIFT	8

#define ID_DFR0_EL1_CopSDbg_SHIFT	4

#define ID_DFR0_EL1_CopDbg_SHIFT	0



#if defined(CONFIG_ARM64_4K_PAGES)

#define ID_AA64MMFR0_EL1_TGRAN_SHIFT		ID_AA64MMFR0_EL1_TGRAN4_SHIFT

#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN	ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN

arch/arm64/tools/sysreg

+50 −0
Original line number Diff line number Diff line
@@ -127,6 +127,56 @@ Enum 3:0 ProgMod 
EndEnum

EndSysreg



Sysreg ID_DFR0_EL1	3	0	0	1	2

Res0	63:32

Enum	31:28	TraceFilt

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	27:24	PerfMon

	0b0000	NI

	0b0001	PMUv1

	0b0010	PMUv2

	0b0011	PMUv3

	0b0100	PMUv3p1

	0b0101	PMUv3p4

	0b0110	PMUv3p5

	0b0111	PMUv3p7

	0b1000	PMUv3p8

	0b1111	IMPDEF

EndEnum

Enum	23:20	MProfDbg

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	19:16	MMapTrc

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	15:12	CopTrc

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	11:8	MMapDbg

	0b0000	NI

	0b0100	Armv7

	0b0101	Armv7p1

EndEnum

Field	7:4	CopSDbg

Enum	3:0	CopDbg

	0b0000	NI

	0b0010	Armv6

	0b0011	Armv6p1

	0b0100	Armv7

	0b0101	Armv7p1

	0b0110	Armv8

	0b0111	VHE

	0b1000	Debugv8p2

	0b1001	Debugv8p4

	0b1010	Debugv8p8

EndEnum

EndSysreg



Sysreg ID_AFR0_EL1	3	0	0	1	3

Res0	63:16

Field	15:12	IMPDEF3