Commit d02dfac3 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
Browse files

coresight: etm4x: Define DEVARCH register fields 

Define the fields of the DEVARCH register for identifying
a component as an ETMv4.x unit. Going forward, we use the
DEVARCH register for the component identification, rather
than the TRCIDR3.

Link: https://lore.kernel.org/r/20210110224850.1880240-14-suzuki.poulose@arm.com


Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-16-mathieu.poirier@linaro.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 91b9f018

drivers/hwtracing/coresight/coresight-etm4x-core.c

+2 −2
Original line number Diff line number Diff line
@@ -1720,8 +1720,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id) 
static struct amba_cs_uci_id uci_id_etm4[] = {

	{

		/*  ETMv4 UCI data */

		.devarch	= 0x47704a13,

		.devarch_mask	= 0xfff0ffff,

		.devarch	= ETM_DEVARCH_ETMv4x_ARCH,

		.devarch_mask	= ETM_DEVARCH_ID_MASK,

		.devtype	= 0x00000013,

	}

};

drivers/hwtracing/coresight/coresight-etm4x.h

+42 −0
Original line number Diff line number Diff line
@@ -506,6 +506,48 @@ 
					 ETM_MODE_EXCL_KERN | \

					 ETM_MODE_EXCL_USER)



/*

 * TRCDEVARCH Bit field definitions

 * Bits[31:21]	- ARCHITECT = Always Arm Ltd.

 *                * Bits[31:28] = 0x4

 *                * Bits[27:21] = 0b0111011

 * Bit[20]	- PRESENT,  Indicates the presence of this register.

 *

 * Bit[19:16]	- REVISION, Revision of the architecture.

 *

 * Bit[15:0]	- ARCHID, Identifies this component as an ETM

 *                * Bits[15:12] - architecture version of ETM

 *                *             = 4 for ETMv4

 *                * Bits[11:0] = 0xA13, architecture part number for ETM.

 */

#define ETM_DEVARCH_ARCHITECT_MASK		GENMASK(31, 21)

#define ETM_DEVARCH_ARCHITECT_ARM		((0x4 << 28) | (0b0111011 << 21))

#define ETM_DEVARCH_PRESENT			BIT(20)

#define ETM_DEVARCH_REVISION_SHIFT		16

#define ETM_DEVARCH_REVISION_MASK		GENMASK(19, 16)

#define ETM_DEVARCH_REVISION(x)			\

	(((x) & ETM_DEVARCH_REVISION_MASK) >> ETM_DEVARCH_REVISION_SHIFT)

#define ETM_DEVARCH_ARCHID_MASK			GENMASK(15, 0)

#define ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT	12

#define ETM_DEVARCH_ARCHID_ARCH_VER_MASK	GENMASK(15, 12)

#define ETM_DEVARCH_ARCHID_ARCH_VER(x)		\

	(((x) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK) >> ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT)



#define ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(ver)			\

	(((ver) << ETM_DEVARCH_ARCHID_ARCH_VER_SHIFT) & ETM_DEVARCH_ARCHID_ARCH_VER_MASK)



#define ETM_DEVARCH_ARCHID_ARCH_PART(x)		((x) & 0xfffUL)



#define ETM_DEVARCH_MAKE_ARCHID(major)			\

	((ETM_DEVARCH_MAKE_ARCHID_ARCH_VER(major)) | ETM_DEVARCH_ARCHID_ARCH_PART(0xA13))



#define ETM_DEVARCH_ARCHID_ETMv4x		ETM_DEVARCH_MAKE_ARCHID(0x4)



#define ETM_DEVARCH_ID_MASK						\

	(ETM_DEVARCH_ARCHITECT_MASK | ETM_DEVARCH_ARCHID_MASK | ETM_DEVARCH_PRESENT)

#define ETM_DEVARCH_ETMv4x_ARCH						\

	(ETM_DEVARCH_ARCHITECT_ARM | ETM_DEVARCH_ARCHID_ETMv4x | ETM_DEVARCH_PRESENT)



#define TRCSTATR_IDLE_BIT		0

#define TRCSTATR_PMSTABLE_BIT		1

#define ETM_DEFAULT_ADDR_COMP		0