Commit d00ffc0c authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/gr/gf100-: port zcull tile mapping calculations from NVGPU 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 5f6474a4

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c

+17 −17
Original line number Diff line number Diff line
@@ -2042,25 +2042,25 @@ gf100_gr_init_zcull(struct gf100_gr *gr) 
{

	struct nvkm_device *device = gr->base.engine.subdev.device;

	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);

	u32 data[TPC_MAX / 8] = {};

	u8  tpcnr[GPC_MAX];

	int gpc, tpc;

	int i;



	memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));

	for (i = 0, gpc = -1; i < gr->tpc_total; i++) {

		do {

			gpc = (gpc + 1) % gr->gpc_nr;

		} while (!tpcnr[gpc]);

		tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;

	const u8 tile_nr = ALIGN(gr->tpc_total, 32);

	u8 bank[GPC_MAX] = {}, gpc, i, j;

	u32 data;



		data[i / 8] |= tpc << ((i % 8) * 4);

	for (i = 0; i < tile_nr; i += 8) {

		for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {

			data |= bank[gr->tile[i + j]] << (j * 4);

			bank[gr->tile[i + j]]++;

		}

		nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);

	}



	nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);

	nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);

	nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);

	nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);

	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),

			  gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);

		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |

							 gr->tpc_total);

		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);

	}



	nvkm_wr32(device, GPC_BCAST(0x1bd4), magicgpc918);

}

drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c

+17 −17
Original line number Diff line number Diff line
@@ -125,25 +125,25 @@ gf117_gr_init_zcull(struct gf100_gr *gr) 
{

	struct nvkm_device *device = gr->base.engine.subdev.device;

	const u32 magicgpc918 = DIV_ROUND_UP(0x00800000, gr->tpc_total);

	u32 data[TPC_MAX / 8] = {};

	u8  tpcnr[GPC_MAX];

	int gpc, tpc;

	int i;



	memcpy(tpcnr, gr->tpc_nr, sizeof(gr->tpc_nr));

	for (i = 0, gpc = -1; i < gr->tpc_total; i++) {

		do {

			gpc = (gpc + 1) % gr->gpc_nr;

		} while (!tpcnr[gpc]);

		tpc = gr->tpc_nr[gpc] - tpcnr[gpc]--;



		data[i / 8] |= tpc << ((i % 8) * 4);

	const u8 tile_nr = ALIGN(gr->tpc_total, 32);

	u8 bank[GPC_MAX] = {}, gpc, i, j;

	u32 data;



	for (i = 0; i < tile_nr; i += 8) {

		for (data = 0, j = 0; j < 8 && i + j < gr->tpc_total; j++) {

			data |= bank[gr->tile[i + j]] << (j * 4);

			bank[gr->tile[i + j]]++;

		}

		nvkm_wr32(device, GPC_BCAST(0x0980 + ((i / 8) * 4)), data);

	}



	nvkm_wr32(device, GPC_BCAST(0x0980), data[0]);

	nvkm_wr32(device, GPC_BCAST(0x0984), data[1]);

	nvkm_wr32(device, GPC_BCAST(0x0988), data[2]);

	nvkm_wr32(device, GPC_BCAST(0x098c), data[3]);

	for (gpc = 0; gpc < gr->gpc_nr; gpc++) {

		nvkm_wr32(device, GPC_UNIT(gpc, 0x0914),

			  gr->screen_tile_row_offset << 8 | gr->tpc_nr[gpc]);

		nvkm_wr32(device, GPC_UNIT(gpc, 0x0910), 0x00040000 |

							 gr->tpc_total);

		nvkm_wr32(device, GPC_UNIT(gpc, 0x0918), magicgpc918);

	}



	nvkm_wr32(device, GPC_BCAST(0x3fd4), magicgpc918);

}