Unverified Commit d007cc92 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!12321 LoongArch: backport 3 patches from upstream 

Merge Pull Request from: @ci-robot 
 
PR sync from: Hongchen Zhang <zhanghongchen@loongson.cn>
https://mailweb.openeuler.org/hyperkitty/list/kernel@openeuler.org/message/ETKWXWLG4ZJE2LTCA4UVBE7CUZFWQZNN/ 
Huacai Chen (3):
  LoongArch: Change SHMLBA from SZ_64K to PAGE_SIZE
  LoongArch: Add writecombine support for DMW-based ioremap()
  LoongArch: Define __ARCH_WANT_NEW_STAT in unistd.h


-- 
2.33.0
 
https://gitee.com/openeuler/kernel/issues/IAZ33N 
 
Link:https://gitee.com/openeuler/kernel/pulls/12321

 

Reviewed-by: default avatarJuxin Gao <gaojuxin@loongson.cn>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 6d5b756b 3e8f269f

arch/loongarch/include/asm/addrspace.h

+4 −0
Original line number Diff line number Diff line
@@ -36,6 +36,10 @@ extern unsigned long vm_map_base; 
#define UNCACHE_BASE		CSR_DMW0_BASE

#endif



#ifndef WRITECOMBINE_BASE

#define WRITECOMBINE_BASE	CSR_DMW2_BASE

#endif



#define DMW_PABITS	48

#define TO_PHYS_MASK	((1ULL << DMW_PABITS) - 1)

arch/loongarch/include/asm/io.h

+8 −2
Original line number Diff line number Diff line
@@ -30,10 +30,16 @@ extern void __init early_iounmap(void __iomem *addr, unsigned long size); 
static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size,

					 unsigned long prot_val)

{

	if (prot_val & _CACHE_CC)

	switch (prot_val & _CACHE_MASK) {

	case _CACHE_CC:

		return (void __iomem *)(unsigned long)(CACHE_BASE + offset);

	else

	case _CACHE_SUC:

		return (void __iomem *)(unsigned long)(UNCACHE_BASE + offset);

	case _CACHE_WUC:

		return (void __iomem *)(unsigned long)(WRITECOMBINE_BASE + offset);

	default:

		return NULL;

	}

}



#define ioremap(offset, size)		\

arch/loongarch/include/asm/loongarch.h

+9 −1
Original line number Diff line number Diff line
@@ -879,7 +879,7 @@ 
#define LOONGARCH_CSR_DMWIN2		0x182	/* 64 direct map win2: MEM */

#define LOONGARCH_CSR_DMWIN3		0x183	/* 64 direct map win3: MEM */



/* Direct Map window 0/1 */

/* Direct Map window 0/1/2/3 */

#define CSR_DMW0_PLV0		_CONST64_(1 << 0)

#define CSR_DMW0_VSEG		_CONST64_(0x8000)

#define CSR_DMW0_BASE		(CSR_DMW0_VSEG << DMW_PABITS)
@@ -891,6 +891,14 @@ 
#define CSR_DMW1_BASE		(CSR_DMW1_VSEG << DMW_PABITS)

#define CSR_DMW1_INIT		(CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0)



#define CSR_DMW2_PLV0		_CONST64_(1 << 0)

#define CSR_DMW2_MAT		_CONST64_(2 << 4)

#define CSR_DMW2_VSEG		_CONST64_(0xa000)

#define CSR_DMW2_BASE		(CSR_DMW2_VSEG << DMW_PABITS)

#define CSR_DMW2_INIT		(CSR_DMW2_BASE | CSR_DMW2_MAT | CSR_DMW2_PLV0)



#define CSR_DMW3_INIT		0x0



/* Performance Counter registers */

#define LOONGARCH_CSR_PERFCTRL0		0x200	/* 32 perf event 0 config */

#define LOONGARCH_CSR_PERFCNTR0		0x201	/* 64 perf event 0 count value */

arch/loongarch/include/asm/shmparam.h

deleted100644 → 0
+0 −12
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited

 */

#ifndef _ASM_SHMPARAM_H

#define _ASM_SHMPARAM_H



#define __ARCH_FORCE_SHMLBA	1



#define	SHMLBA	SZ_64K		 /* attach addr a multiple of this */



#endif /* _ASM_SHMPARAM_H */

arch/loongarch/include/asm/stackframe.h

+11 −0
Original line number Diff line number Diff line
@@ -37,6 +37,17 @@ 
	cfi_restore \reg \offset \docfi

	.endm



	.macro SETUP_DMWINS temp

	li.d	\temp, CSR_DMW0_INIT	# WUC, PLV0, 0x8000 xxxx xxxx xxxx

	csrwr	\temp, LOONGARCH_CSR_DMWIN0

	li.d	\temp, CSR_DMW1_INIT	# CAC, PLV0, 0x9000 xxxx xxxx xxxx

	csrwr	\temp, LOONGARCH_CSR_DMWIN1

	li.d	\temp, CSR_DMW2_INIT	# WUC, PLV0, 0xa000 xxxx xxxx xxxx

	csrwr	\temp, LOONGARCH_CSR_DMWIN2

	li.d	\temp, CSR_DMW3_INIT	# 0x0, unused

	csrwr	\temp, LOONGARCH_CSR_DMWIN3

	.endm



/* Jump to the runtime virtual address. */

	.macro JUMP_VIRT_ADDR temp1 temp2

	li.d	\temp1, CACHE_BASE