Commit cfdd30b4 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

Merge tag 'gvt-next-2020-02-26' of https://github.com/intel/gvt-linux into drm-intel-next-queued 



gvt-next-2020-02-26

- Enable VFIO edid for all platform (Zhenyu)
- Code cleanup for attr group and unused vblank complete (Zhenyu, Julian)
- Make gvt oblivious of kvmgt data structures (Julian)
- Make WARN* drm specific (Pankaj)

Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200226103840.GD10413@zhen-hp.sh.intel.com
parents 7a0a6ee7 a8bb49b6

drivers/gpu/drm/i915/gvt/aperture_gm.c

+3 −3
Original line number Diff line number Diff line
@@ -134,11 +134,11 @@ void intel_vgpu_write_fence(struct intel_vgpu *vgpu, 


	assert_rpm_wakelock_held(&dev_priv->runtime_pm);



	if (WARN_ON(fence >= vgpu_fence_sz(vgpu)))

	if (drm_WARN_ON(&dev_priv->drm, fence >= vgpu_fence_sz(vgpu)))

		return;



	reg = vgpu->fence.regs[fence];

	if (WARN_ON(!reg))

	if (drm_WARN_ON(&dev_priv->drm, !reg))

		return;



	fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
@@ -167,7 +167,7 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu) 
	struct i915_fence_reg *reg;

	u32 i;



	if (WARN_ON(!vgpu_fence_sz(vgpu)))

	if (drm_WARN_ON(&dev_priv->drm, !vgpu_fence_sz(vgpu)))

		return;



	intel_runtime_pm_get(&dev_priv->runtime_pm);

drivers/gpu/drm/i915/gvt/cfg_space.c

+14 −9
Original line number Diff line number Diff line
@@ -106,10 +106,13 @@ static void vgpu_pci_cfg_mem_write(struct intel_vgpu *vgpu, unsigned int off, 
int intel_vgpu_emulate_cfg_read(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	if (WARN_ON(bytes > 4))

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;



	if (drm_WARN_ON(&i915->drm, bytes > 4))

		return -EINVAL;



	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))

	if (drm_WARN_ON(&i915->drm,

			offset + bytes > vgpu->gvt->device_info.cfg_space_size))

		return -EINVAL;



	memcpy(p_data, vgpu_cfg_space(vgpu) + offset, bytes);
@@ -297,34 +300,36 @@ static int emulate_pci_bar_write(struct intel_vgpu *vgpu, unsigned int offset, 
int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset,

	void *p_data, unsigned int bytes)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	int ret;



	if (WARN_ON(bytes > 4))

	if (drm_WARN_ON(&i915->drm, bytes > 4))

		return -EINVAL;



	if (WARN_ON(offset + bytes > vgpu->gvt->device_info.cfg_space_size))

	if (drm_WARN_ON(&i915->drm,

			offset + bytes > vgpu->gvt->device_info.cfg_space_size))

		return -EINVAL;



	/* First check if it's PCI_COMMAND */

	if (IS_ALIGNED(offset, 2) && offset == PCI_COMMAND) {

		if (WARN_ON(bytes > 2))

		if (drm_WARN_ON(&i915->drm, bytes > 2))

			return -EINVAL;

		return emulate_pci_command_write(vgpu, offset, p_data, bytes);

	}



	switch (rounddown(offset, 4)) {

	case PCI_ROM_ADDRESS:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		return emulate_pci_rom_bar_write(vgpu, offset, p_data, bytes);



	case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_5:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		return emulate_pci_bar_write(vgpu, offset, p_data, bytes);



	case INTEL_GVT_PCI_SWSCI:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		ret = intel_vgpu_emulate_opregion_request(vgpu, *(u32 *)p_data);

		if (ret)
@@ -332,7 +337,7 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
		break;



	case INTEL_GVT_PCI_OPREGION:

		if (WARN_ON(!IS_ALIGNED(offset, 4)))

		if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4)))

			return -EINVAL;

		ret = intel_vgpu_opregion_base_write_handler(vgpu,

						   *(u32 *)p_data);

drivers/gpu/drm/i915/gvt/cmd_parser.c

+2 −2
Original line number Diff line number Diff line
@@ -1230,7 +1230,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 
	dword2 = cmd_val(s, 2);



	v = (dword0 & GENMASK(21, 19)) >> 19;

	if (WARN_ON(v >= ARRAY_SIZE(gen8_plane_code)))

	if (drm_WARN_ON(&dev_priv->drm, v >= ARRAY_SIZE(gen8_plane_code)))

		return -EBADRQC;



	info->pipe = gen8_plane_code[v].pipe;
@@ -1250,7 +1250,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, 
		info->stride_reg = SPRSTRIDE(info->pipe);

		info->surf_reg = SPRSURF(info->pipe);

	} else {

		WARN_ON(1);

		drm_WARN_ON(&dev_priv->drm, 1);

		return -EBADRQC;

	}

	return 0;

drivers/gpu/drm/i915/gvt/display.c

+4 −2
Original line number Diff line number Diff line
@@ -71,7 +71,8 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))

	if (drm_WARN_ON(&dev_priv->drm,

			pipe < PIPE_A || pipe >= I915_MAX_PIPES))

		return -EINVAL;



	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
@@ -319,9 +320,10 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 
static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,

				    int type, unsigned int resolution)

{

	struct drm_i915_private *i915 = vgpu->gvt->dev_priv;

	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);



	if (WARN_ON(resolution >= GVT_EDID_NUM))

	if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))

		return -EINVAL;



	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);

drivers/gpu/drm/i915/gvt/dmabuf.c

+2 −2
Original line number Diff line number Diff line
@@ -67,11 +67,11 @@ static int vgpu_gem_get_pages( 
	u32 page_num;



	fb_info = (struct intel_vgpu_fb_info *)obj->gvt_info;

	if (WARN_ON(!fb_info))

	if (drm_WARN_ON(&dev_priv->drm, !fb_info))

		return -ENODEV;



	vgpu = fb_info->obj->vgpu;

	if (WARN_ON(!vgpu))

	if (drm_WARN_ON(&dev_priv->drm, !vgpu))

		return -ENODEV;



	st = kmalloc(sizeof(*st), GFP_KERNEL);