Commit cfa20498 authored Apr 14, 2020 by Mauro Carvalho Chehab Committed by Jonathan Corbet Apr 20, 2020

docs: ras: get rid of some warnings

Sphinx produce some warnings due to a bad table format:

Documentation/admin-guide/ras.rst:358: WARNING: Definition list ends without a blank line; unexpected unindent.
Documentation/admin-guide/ras.rst:358: WARNING: Definition list ends without a blank line; unexpected unindent.
Documentation/admin-guide/ras.rst:363: WARNING: Definition list ends without a blank line; unexpected unindent.
Documentation/admin-guide/ras.rst:363: WARNING: Definition list ends without a blank line; unexpected unindent.

Rearrange the things there in order to supress the warnings
while being precise at the Sphinx output about how ranks are
mapped into csrows.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/9e1bb44d6dbedb5b6f049d081b47da1f9620de16.1586881715.git.mchehab+huawei@kernel.org

Signed-off-by: Jonathan Corbet <corbet@lwn.net>

parent a588332f

Documentation/admin-guide/ras.rst

+9 −7

Original line number	Diff line number	Diff line
		@@ -351,14 +351,16 @@ controllers. The following example will assume 2 channels:
		+------------+-----------+-----------+
		\| \| ``ch0`` \| ``ch1`` \|
		+============+===========+===========+
		\| ``csrow0`` \| DIMM_A0 \| DIMM_B0 \|
		\| \| rank0 \| rank0 \|
		+------------+ - \| - \|
		\| \|DIMM_A0\|DIMM_B0\|
		+------------+-----------+-----------+
		\| ``csrow0`` \| rank0 \| rank0 \|
		+------------+-----------+-----------+
		\| ``csrow1`` \| rank1 \| rank1 \|
		+------------+-----------+-----------+
		\| ``csrow2`` \| DIMM_A1 \| DIMM_B1 \|
		\| \| rank0 \| rank0 \|
		+------------+ - \| - \|
		\| \|DIMM_A1\|DIMM_B1\|
		+------------+-----------+-----------+
		\| ``csrow2`` \| rank0 \| rank0 \|
		+------------+-----------+-----------+
		\| ``csrow3`` \| rank1 \| rank1 \|
		+------------+-----------+-----------+

Original line number	Diff line number	Diff line
		@@ -351,14 +351,16 @@ controllers. The following example will assume 2 channels:
		+------------+-----------+-----------+
		\| \| ``ch0`` \| ``ch1`` \|
		+============+===========+===========+
		\| ``csrow0`` \| DIMM_A0 \| DIMM_B0 \|
		\| \| rank0 \| rank0 \|
		+------------+ - \| - \|
		\| \|DIMM_A0\|DIMM_B0\|
		+------------+-----------+-----------+
		\| ``csrow0`` \| rank0 \| rank0 \|
		+------------+-----------+-----------+
		\| ``csrow1`` \| rank1 \| rank1 \|
		+------------+-----------+-----------+
		\| ``csrow2`` \| DIMM_A1 \| DIMM_B1 \|
		\| \| rank0 \| rank0 \|
		+------------+ - \| - \|
		\| \|DIMM_A1\|DIMM_B1\|
		+------------+-----------+-----------+
		\| ``csrow2`` \| rank0 \| rank0 \|
		+------------+-----------+-----------+
		\| ``csrow3`` \| rank1 \| rank1 \|
		+------------+-----------+-----------+