Commit cf97c5e0 authored by Lukas Wunner's avatar Lukas Wunner Committed by Greg Kroah-Hartman
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xhci: Preserve RsvdP bits in ERSTBA register correctly



xhci_add_interrupter() erroneously preserves only the lowest 4 bits when
writing the ERSTBA register, not the lowest 6 bits.  Fix it.

Migrate the ERST_BASE_RSVDP macro to the modern GENMASK_ULL() syntax to
avoid a u64 cast.

This was previously fixed by commit 8c1cbec9 ("xhci: fix event ring
segment table related masks and variables in header"), but immediately
undone by commit b17a57f8 ("xhci: Refactor interrupter code for
initial multi interrupter support.").

Fixes: b17a57f8 ("xhci: Refactor interrupter code for initial multi interrupter support.")
Signed-off-by: default avatarLukas Wunner <lukas@wunner.de>
Cc: stable@vger.kernel.org # v6.3+
Signed-off-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20230915143108.1532163-5-mathias.nyman@linux.intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 15f3ef07
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+2 −2
Original line number Diff line number Diff line
@@ -2285,8 +2285,8 @@ xhci_add_interrupter(struct xhci_hcd *xhci, struct xhci_interrupter *ir,
	writel(erst_size, &ir->ir_set->erst_size);

	erst_base = xhci_read_64(xhci, &ir->ir_set->erst_base);
	erst_base &= ERST_PTR_MASK;
	erst_base |= (ir->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
	erst_base &= ERST_BASE_RSVDP;
	erst_base |= ir->erst.erst_dma_addr & ~ERST_BASE_RSVDP;
	xhci_write_64(xhci, erst_base, &ir->ir_set->erst_base);

	/* Set the event ring dequeue address of this interrupter */
+1 −1
Original line number Diff line number Diff line
@@ -514,7 +514,7 @@ struct xhci_intr_reg {
#define	ERST_SIZE_MASK		(0xffff << 16)

/* erst_base bitmasks */
#define ERST_BASE_RSVDP		(0x3f)
#define ERST_BASE_RSVDP		(GENMASK_ULL(5, 0))

/* erst_dequeue bitmasks */
/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)