Commit cf9695d8 authored by Clément Léger's avatar Clément Léger Committed by David S. Miller
Browse files

ARM: dts: r9a06g032: describe switch 



Add description of the switch that is present on the RZ/N1 SoC. This
description includes ethernet-ports description for all the ports that
are present on the switch along with their connection to the MII
converter ports and to the GMAC for the CPU port.

Signed-off-by: default avatarClément Léger <clement.leger@bootlin.com>
Reviewed-by: default avatarVladimir Oltean <olteanv@gmail.com>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3f5261f1

arch/arm/boot/dts/r9a06g032.dtsi

+51 −0
Original line number Diff line number Diff line
@@ -361,6 +361,57 @@ 
			};

		};



		switch: switch@44050000 {

			compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw";

			reg = <0x44050000 0x10000>;

			clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,

				 <&sysctrl R9A06G032_CLK_SWITCH>;

			clock-names = "hclk", "clk";

			power-domains = <&sysctrl>;

			status = "disabled";



			ethernet-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				switch_port0: port@0 {

					reg = <0>;

					pcs-handle = <&mii_conv5>;

					status = "disabled";

				};



				switch_port1: port@1 {

					reg = <1>;

					pcs-handle = <&mii_conv4>;

					status = "disabled";

				};



				switch_port2: port@2 {

					reg = <2>;

					pcs-handle = <&mii_conv3>;

					status = "disabled";

				};



				switch_port3: port@3 {

					reg = <3>;

					pcs-handle = <&mii_conv2>;

					status = "disabled";

				};



				switch_port4: port@4 {

					reg = <4>;

					ethernet = <&gmac2>;

					label = "cpu";

					phy-mode = "internal";

					status = "disabled";

					fixed-link {

						speed = <1000>;

						full-duplex;

					};

				};

			};

		};



		gic: interrupt-controller@44101000 {

			compatible = "arm,gic-400", "arm,cortex-a7-gic";

			interrupt-controller;