Commit cf9420cb authored by Radhakrishna Sripada's avatar Radhakrishna Sripada Committed by José Roberto de Souza
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drm/i915: Fix Memory BW formulae for ADL-P 



The earlier update to BW formulae broke ADL-P. Include
display 13 to use TGL path for BW parameters.

Fixes: c64a9a7c ("drm/i915: Update memory bandwidth formulae")
Cc: Matt Roper <matthew.d.roper@intel.com>
Reported-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: default avatarCaz Yokoyama <caz.yokoyama@intel.com>
Reviewed-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211106003714.17894-1-radhakrishna.sripada@intel.com
parent 4fe7907f

drivers/gpu/drm/i915/display/intel_bw.c

+1 −1
Original line number Diff line number Diff line
@@ -147,7 +147,7 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, 
	qi->num_points = dram_info->num_qgv_points;

	qi->num_psf_points = dram_info->num_psf_gv_points;



	if (DISPLAY_VER(dev_priv) == 12)

	if (DISPLAY_VER(dev_priv) >= 12)

		switch (dram_info->type) {

		case INTEL_DRAM_DDR4:

			qi->t_bl = is_y_tile ? 8 : 4;