Commit cf8fc2a0 authored by Bruce Allan's avatar Bruce Allan Committed by Jeff Kirsher
Browse files

ice: update Unit Load Status bitmask to check after reset 



After a reset the Unit Load Status bits in the GLNVM_ULD register to check
for completion should be 0x7FF before continuing.  Update the mask to check
(minus the three reserved bits that are always set).

Signed-off-by: default avatarBruce Allan <bruce.w.allan@intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
Tested-by: default avatarAndrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent fbf1e1f6

drivers/net/ethernet/intel/ice/ice_common.c

+12 −5
Original line number Diff line number Diff line
@@ -818,7 +818,7 @@ void ice_deinit_hw(struct ice_hw *hw) 
 */

enum ice_status ice_check_reset(struct ice_hw *hw)

{

	u32 cnt, reg = 0, grst_delay;

	u32 cnt, reg = 0, grst_delay, uld_mask;



	/* Poll for Device Active state in case a recent CORER, GLOBR,

	 * or EMPR has occurred. The grst delay value is in 100ms units.
@@ -840,13 +840,20 @@ enum ice_status ice_check_reset(struct ice_hw *hw) 
		return ICE_ERR_RESET_FAILED;

	}



#define ICE_RESET_DONE_MASK	(GLNVM_ULD_CORER_DONE_M | \

				 GLNVM_ULD_GLOBR_DONE_M)

#define ICE_RESET_DONE_MASK	(GLNVM_ULD_PCIER_DONE_M |\

				 GLNVM_ULD_PCIER_DONE_1_M |\

				 GLNVM_ULD_CORER_DONE_M |\

				 GLNVM_ULD_GLOBR_DONE_M |\

				 GLNVM_ULD_POR_DONE_M |\

				 GLNVM_ULD_POR_DONE_1_M |\

				 GLNVM_ULD_PCIER_DONE_2_M)



	uld_mask = ICE_RESET_DONE_MASK;



	/* Device is Active; check Global Reset processes are done */

	for (cnt = 0; cnt < ICE_PF_RESET_WAIT_COUNT; cnt++) {

		reg = rd32(hw, GLNVM_ULD) & ICE_RESET_DONE_MASK;

		if (reg == ICE_RESET_DONE_MASK) {

		reg = rd32(hw, GLNVM_ULD) & uld_mask;

		if (reg == uld_mask) {

			ice_debug(hw, ICE_DBG_INIT,

				  "Global reset processes done. %d\n", cnt);

			break;

drivers/net/ethernet/intel/ice/ice_hw_autogen.h

+6 −0
Original line number Diff line number Diff line
@@ -267,8 +267,14 @@ 
#define GLNVM_GENS_SR_SIZE_S			5

#define GLNVM_GENS_SR_SIZE_M			ICE_M(0x7, 5)

#define GLNVM_ULD				0x000B6008

#define GLNVM_ULD_PCIER_DONE_M			BIT(0)

#define GLNVM_ULD_PCIER_DONE_1_M		BIT(1)

#define GLNVM_ULD_CORER_DONE_M			BIT(3)

#define GLNVM_ULD_GLOBR_DONE_M			BIT(4)

#define GLNVM_ULD_POR_DONE_M			BIT(5)

#define GLNVM_ULD_POR_DONE_1_M			BIT(8)

#define GLNVM_ULD_PCIER_DONE_2_M		BIT(9)

#define GLNVM_ULD_PE_DONE_M			BIT(10)

#define GLPCI_CNF2				0x000BE004

#define GLPCI_CNF2_CACHELINE_SIZE_M		BIT(1)

#define PF_FUNC_RID				0x0009E880