Commit cf8dccfe authored by Peng Fan's avatar Peng Fan Committed by Abel Vesa
Browse files

clk: imx: fracn-gppll: fix the rate table 



The Fvco should be range 2.4GHz to 5GHz, the original table voilate the
spec, so update the table to fix it.

Fixes: c196175a ("clk: imx: clk-fracn-gppll: Add more freq config for video pll")
Fixes: 044034ef ("clk: imx: clk-fracn-gppll: fix mfd value")
Fixes: 1b26cb8a ("clk: imx: support fracn gppll")
Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230403095300.3386988-2-peng.fan@oss.nxp.com


Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
parent 7875ee29

drivers/clk/imx/clk-fracn-gppll.c

+9 −7
Original line number Diff line number Diff line
@@ -60,18 +60,20 @@ struct clk_fracn_gppll { 
};



/*

 * Fvco = Fref * (MFI + MFN / MFD)

 * Fout = Fvco / (rdiv * odiv)

 * Fvco = (Fref / rdiv) * (MFI + MFN / MFD)

 * Fout = Fvco / odiv

 * The (Fref / rdiv) should be in range 20MHz to 40MHz

 * The Fvco should be in range 2.5Ghz to 5Ghz

 */

static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {

	PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3),

	PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),

	PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),

	PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3),

	PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4),

	PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),

	PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),

	PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),

	PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),

	PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3),

	PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5)

	PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),

	PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10)

};



struct imx_fracn_gppll_clk imx_fracn_gppll = {