Commit cf8a82de authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915/selftests: Run MI_BB perf selftests on SNB 



SNB does have the RING_TIMESTAMP register on the RCS engine.
Run the MI_BB perf tests on it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221031135703.14670-5-ville.syrjala@linux.intel.com


Reviewed-by: default avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
parent dbea79a5

drivers/gpu/drm/i915/gt/selftest_engine_cs.c

+8 −2
Original line number Diff line number Diff line
@@ -125,7 +125,7 @@ static int perf_mi_bb_start(void *arg) 
	enum intel_engine_id id;

	int err = 0;



	if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */

	if (GRAPHICS_VER(gt->i915) < 6) /* for per-engine CS_TIMESTAMP */

		return 0;



	perf_begin(gt);
@@ -135,6 +135,9 @@ static int perf_mi_bb_start(void *arg) 
		u32 cycles[COUNT];

		int i;



		if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)

			continue;



		intel_engine_pm_get(engine);



		batch = create_empty_batch(ce);
@@ -249,7 +252,7 @@ static int perf_mi_noop(void *arg) 
	enum intel_engine_id id;

	int err = 0;



	if (GRAPHICS_VER(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */

	if (GRAPHICS_VER(gt->i915) < 6) /* for per-engine CS_TIMESTAMP */

		return 0;



	perf_begin(gt);
@@ -259,6 +262,9 @@ static int perf_mi_noop(void *arg) 
		u32 cycles[COUNT];

		int i;



		if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0)

			continue;



		intel_engine_pm_get(engine);



		base = create_empty_batch(ce);