Commit cf87691f authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
Browse files

clk: rockchip: add register offset of the cores select parent 



The cores select parent register is special on RK3588.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarSebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 4f5ca304

drivers/clk/rockchip/clk-cpu.c

+20 −8
Original line number Diff line number Diff line
@@ -166,6 +166,12 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk, 
		}

	}

	/* select alternate parent */

	if (reg_data->mux_core_reg)

		writel(HIWORD_UPDATE(reg_data->mux_core_alt,

				     reg_data->mux_core_mask,

				     reg_data->mux_core_shift),

		       cpuclk->reg_base + reg_data->mux_core_reg);

	else

		writel(HIWORD_UPDATE(reg_data->mux_core_alt,

				     reg_data->mux_core_mask,

				     reg_data->mux_core_shift),
@@ -202,6 +208,12 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk, 
	 * primary parent by the extra dividers that were needed for the alt.

	 */



	if (reg_data->mux_core_reg)

		writel(HIWORD_UPDATE(reg_data->mux_core_main,

				     reg_data->mux_core_mask,

				     reg_data->mux_core_shift),

		       cpuclk->reg_base + reg_data->mux_core_reg);

	else

		writel(HIWORD_UPDATE(reg_data->mux_core_main,

				     reg_data->mux_core_mask,

				     reg_data->mux_core_shift),

drivers/clk/rockchip/clk.h

+3 −0
Original line number Diff line number Diff line
@@ -389,6 +389,8 @@ struct rockchip_cpuclk_rate_table { 
 * @div_core_shift[]:	cores divider offset used to divide the pll value

 * @div_core_mask[]:	cores divider mask

 * @num_cores:	number of cpu cores

 * @mux_core_reg:       register offset of the cores select parent

 * @mux_core_alt:       mux value to select alternate parent

 * @mux_core_main:	mux value to select main parent of core

 * @mux_core_shift:	offset of the core multiplexer

 * @mux_core_mask:	core multiplexer mask
@@ -398,6 +400,7 @@ struct rockchip_cpuclk_reg_data { 
	u8	div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];

	u32	div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];

	int	num_cores;

	int	mux_core_reg;

	u8	mux_core_alt;

	u8	mux_core_main;

	u8	mux_core_shift;