Commit cf83a28f authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation 



UART clock is divided using divisor values from DLM/DLL registers when
enable-bit is unset in clk register and clk's divider configuration isn't
taken onto account in this case. This doesn't cause any problems, but
let's add a check for the divider's enable-bit state, for consistency.

Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent d8edf528

drivers/clk/tegra/clk-divider.c

+7 −2
Original line number Diff line number Diff line
@@ -40,8 +40,13 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw, 
	int div, mul;

	u64 rate = parent_rate;



	reg = readl_relaxed(divider->reg) >> divider->shift;

	div = reg & div_mask(divider);

	reg = readl_relaxed(divider->reg);



	if ((divider->flags & TEGRA_DIVIDER_UART) &&

	    !(reg & PERIPH_CLK_UART_DIV_ENB))

		return rate;



	div = (reg >> divider->shift) & div_mask(divider);



	mul = get_mul(divider);

	div += mul;