Commit cf5e7fb0 authored Mar 03, 2025 by Huacai Chen Committed by Hongchen Zhang Mar 03, 2025

LoongArch: Correct the cacheinfo sharing information

mainline inclusion
from mainline-v6.14-rc1
commit b62a03049f141061d0397bfa86b74f65985d9338
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IBQ4JL
CVE: NA
Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b62a03049f141061d0397bfa86b74f65985d9338



--------------------------------

SMT cores and their sibling cores share the same L1 and L2 private
caches (of course last level cache is also shared), so correct the
cacheinfo sharing information to let shared_cpu_map correctly reflect
this relationship.

Below is the output of "lscpu" on Loongson-3A6000 (4 cores, 8 threads).

1. Before patch:

  L1d:                    512 KiB (8 instances)
  L1i:                    512 KiB (8 instances)
  L2:                     2 MiB (8 instances)
  L3:                     16 MiB (1 instance)

2. After patch:

  L1d:                    256 KiB (4 instances)
  L1i:                    256 KiB (4 instances)
  L2:                     1 MiB (4 instances)
  L3:                     16 MiB (1 instance)

Change-Id: I6e07913c76bad6a120454510b3f4f8ecaef796f2
Reported-by: Chao Li <lichao@loongson.cn>
Signed-off-by: Juxin Gao <gaojuxin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>

parent 6b1d9f42

arch/loongarch/kernel/cacheinfo.c

+6 −0

Original line number	Diff line number	Diff line
		@@ -51,6 +51,12 @@ static void cache_cpumap_setup(unsigned int cpu)
		continue;

		sib_leaf = sib_cpu_ci->info_list + index;
		/* SMT cores share all caches */
		if (cpus_are_siblings(i, cpu)) {
		cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
		cpumask_set_cpu(i, &this_leaf->shared_cpu_map);
		}
		/* Node's cores share shared caches */
		if (cache_leaves_are_shared(this_leaf, sib_leaf)) {
		cpumask_set_cpu(cpu, &sib_leaf->shared_cpu_map);
		cpumask_set_cpu(i, &this_leaf->shared_cpu_map);