Commit cf27a6d1 authored by Eric Yang's avatar Eric Yang Committed by Alex Deucher
Browse files

drm/amd/display: update chroma viewport wa 



[Why]
Need previously implemented chroma vp wa to work for rotation cases.

[How]
Implement rotation specific wa.

Signed-off-by: default avatarEric Yang <Eric.Yang2@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0120e8b8

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c

+1 −2
Original line number Diff line number Diff line
@@ -810,8 +810,7 @@ static void hubp1_set_vm_context0_settings(struct hubp *hubp, 
void min_set_viewport(

	struct hubp *hubp,

	const struct rect *viewport,

	const struct rect *viewport_c,

	enum dc_rotation_angle rotation)

	const struct rect *viewport_c)

{

	struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h

+1 −3
Original line number Diff line number Diff line
@@ -749,9 +749,7 @@ void hubp1_set_blank(struct hubp *hubp, bool blank); 


void min_set_viewport(struct hubp *hubp,

		const struct rect *viewport,

		const struct rect *viewport_c,

		enum dc_rotation_angle rotation);

/* rotation angle added for use by hubp21_set_viewport */

		const struct rect *viewport_c);



void hubp1_clk_cntl(struct hubp *hubp, bool enable);

void hubp1_vtg_sel(struct hubp *hubp, uint32_t otg_inst);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+1 −2
Original line number Diff line number Diff line
@@ -2291,8 +2291,7 @@ static void dcn10_update_dchubp_dpp( 
		hubp->funcs->mem_program_viewport(

			hubp,

			&pipe_ctx->plane_res.scl_data.viewport,

			&pipe_ctx->plane_res.scl_data.viewport_c,

			plane_state->rotation);

			&pipe_ctx->plane_res.scl_data.viewport_c);

	}



	if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+11 −3
Original line number Diff line number Diff line
@@ -1305,6 +1305,7 @@ static void dcn20_update_dchubp_dpp( 
	struct hubp *hubp = pipe_ctx->plane_res.hubp;

	struct dpp *dpp = pipe_ctx->plane_res.dpp;

	struct dc_plane_state *plane_state = pipe_ctx->plane_state;

	bool viewport_changed = false;



	if (pipe_ctx->update_flags.bits.dppclk)

		dpp->funcs->dpp_dppclk_control(dpp, false, true);
@@ -1383,12 +1384,14 @@ static void dcn20_update_dchubp_dpp( 


	if (pipe_ctx->update_flags.bits.viewport ||

			(context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||

			(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling))

			(context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {



		hubp->funcs->mem_program_viewport(

			hubp,

			&pipe_ctx->plane_res.scl_data.viewport,

			&pipe_ctx->plane_res.scl_data.viewport_c,

			plane_state->rotation);

			&pipe_ctx->plane_res.scl_data.viewport_c);

		viewport_changed = true;

	}



	/* Any updates are handled in dc interface, just need to apply existing for plane enable */

	if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed)
@@ -1441,9 +1444,14 @@ static void dcn20_update_dchubp_dpp( 
		hubp->power_gated = false;

	}



	if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed)

		hubp->funcs->apply_PLAT_54186_wa(hubp, &plane_state->address);



	if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)

		hws->funcs.update_plane_addr(dc, pipe_ctx);







	if (pipe_ctx->update_flags.bits.enable)

		hubp->funcs->set_blank(hubp, false);

}

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c

+286 −28
Original line number Diff line number Diff line
@@ -169,12 +169,9 @@ static void hubp21_setup( 
void hubp21_set_viewport(

	struct hubp *hubp,

	const struct rect *viewport,

	const struct rect *viewport_c,

	enum dc_rotation_angle rotation)

	const struct rect *viewport_c)

{

	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

	int patched_viewport_height = 0;

	struct dc_debug_options *debug = &hubp->ctx->dc->debug;



	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION, 0,

		  PRI_VIEWPORT_WIDTH, viewport->width,
@@ -193,31 +190,10 @@ void hubp21_set_viewport( 
		  SEC_VIEWPORT_X_START, viewport->x,

		  SEC_VIEWPORT_Y_START, viewport->y);



	/*

	 *	Work around for underflow issue with NV12 + rIOMMU translation

	 *	+ immediate flip. This will cause hubp underflow, but will not

	 *	be user visible since underflow is in blank region

	 *	Disable w/a when rotated 180 degrees, causes vertical chroma offset

	 */

	patched_viewport_height = viewport_c->height;

	if (debug->nv12_iflip_vm_wa && viewport_c->height > 512 &&

			rotation != ROTATION_ANGLE_180) {

		int pte_row_height = 0;

		int pte_rows = 0;



		REG_GET(DCHUBP_REQ_SIZE_CONFIG_C,

			PTE_ROW_HEIGHT_LINEAR_C, &pte_row_height);



		pte_row_height = 1 << (pte_row_height + 3);

		pte_rows = (viewport_c->height / pte_row_height) + 1;

		patched_viewport_height = pte_rows * pte_row_height + 1;

	}





	/* DC supports NV12 only at the moment */

	REG_SET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C, 0,

		  PRI_VIEWPORT_WIDTH_C, viewport_c->width,

		  PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);

		  PRI_VIEWPORT_HEIGHT_C, viewport_c->height);



	REG_SET_2(DCSURF_PRI_VIEWPORT_START_C, 0,

		  PRI_VIEWPORT_X_START_C, viewport_c->x,
@@ -225,13 +201,113 @@ void hubp21_set_viewport( 


	REG_SET_2(DCSURF_SEC_VIEWPORT_DIMENSION_C, 0,

		  SEC_VIEWPORT_WIDTH_C, viewport_c->width,

		  SEC_VIEWPORT_HEIGHT_C, patched_viewport_height);

		  SEC_VIEWPORT_HEIGHT_C, viewport_c->height);



	REG_SET_2(DCSURF_SEC_VIEWPORT_START_C, 0,

		  SEC_VIEWPORT_X_START_C, viewport_c->x,

		  SEC_VIEWPORT_Y_START_C, viewport_c->y);

}



static void hubp21_apply_PLAT_54186_wa(

		struct hubp *hubp,

		const struct dc_plane_address *address)

{

	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

	struct dc_debug_options *debug = &hubp->ctx->dc->debug;

	unsigned int chroma_bpe = 2;

	unsigned int luma_addr_high_part = 0;

	unsigned int row_height = 0;

	unsigned int chroma_pitch = 0;

	unsigned int viewport_c_height = 0;

	unsigned int viewport_c_width = 0;

	unsigned int patched_viewport_height = 0;

	unsigned int patched_viewport_width = 0;

	unsigned int rotation_angle = 0;

	unsigned int pix_format = 0;

	unsigned int h_mirror_en = 0;

	unsigned int tile_blk_size = 64 * 1024; /* 64KB for 64KB SW, 4KB for 4KB SW */





	if (!debug->nv12_iflip_vm_wa)

		return;



	REG_GET(DCHUBP_REQ_SIZE_CONFIG_C,

		PTE_ROW_HEIGHT_LINEAR_C, &row_height);



	REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION_C,

			PRI_VIEWPORT_WIDTH_C, &viewport_c_width,

			PRI_VIEWPORT_HEIGHT_C, &viewport_c_height);



	REG_GET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C,

			PRIMARY_SURFACE_ADDRESS_HIGH_C, &luma_addr_high_part);



	REG_GET(DCSURF_SURFACE_PITCH_C,

			PITCH_C, &chroma_pitch);



	chroma_pitch += 1;



	REG_GET_3(DCSURF_SURFACE_CONFIG,

			SURFACE_PIXEL_FORMAT, &pix_format,

			ROTATION_ANGLE, &rotation_angle,

			H_MIRROR_EN, &h_mirror_en);



	/* apply wa only for NV12 surface with scatter gather enabled with view port > 512 */

	if (address->type != PLN_ADDR_TYPE_VIDEO_PROGRESSIVE ||

			address->video_progressive.luma_addr.high_part == 0xf4

			|| viewport_c_height <= 512)

		return;



	switch (rotation_angle) {

	case 0: /* 0 degree rotation */

		row_height = 128;

		patched_viewport_height = (viewport_c_height / row_height + 1) * row_height + 1;

		patched_viewport_width = viewport_c_width;

		hubp21->PLAT_54186_wa_chroma_addr_offset = 0;

		break;

	case 2: /* 180 degree rotation */

		row_height = 128;

		patched_viewport_height = viewport_c_height + row_height;

		patched_viewport_width = viewport_c_width;

		hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - chroma_pitch * row_height * chroma_bpe;

		break;

	case 1: /* 90 degree rotation */

		row_height = 256;

		if (h_mirror_en) {

			patched_viewport_height = viewport_c_height;

			patched_viewport_width = viewport_c_width + row_height;

			hubp21->PLAT_54186_wa_chroma_addr_offset = 0;

		} else {

			patched_viewport_height = viewport_c_height;

			patched_viewport_width = viewport_c_width + row_height;

			hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size;

		}

		break;

	case 3:	/* 270 degree rotation */

		row_height = 256;

		if (h_mirror_en) {

			patched_viewport_height = viewport_c_height;

			patched_viewport_width = viewport_c_width + row_height;

			hubp21->PLAT_54186_wa_chroma_addr_offset = 0 - tile_blk_size;

		} else {

			patched_viewport_height = viewport_c_height;

			patched_viewport_width = viewport_c_width + row_height;

			hubp21->PLAT_54186_wa_chroma_addr_offset = 0;

		}

		break;

	default:

		ASSERT(0);

		break;

	}



	/* catch cases where viewport keep growing */

	ASSERT(patched_viewport_height && patched_viewport_height < 5000);

	ASSERT(patched_viewport_width && patched_viewport_width < 5000);



	REG_UPDATE_2(DCSURF_PRI_VIEWPORT_DIMENSION_C,

			PRI_VIEWPORT_WIDTH_C, patched_viewport_width,

			PRI_VIEWPORT_HEIGHT_C, patched_viewport_height);

}



void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,

		struct vm_system_aperture_param *apt)

{
@@ -602,6 +678,187 @@ void hubp21_validate_dml_output(struct hubp *hubp, 
				dml_dlg_attr->refcyc_per_meta_chunk_flip_l, dlg_attr.refcyc_per_meta_chunk_flip_l);

}



bool hubp21_program_surface_flip_and_addr(

	struct hubp *hubp,

	const struct dc_plane_address *address,

	bool flip_immediate)

{

	struct dcn21_hubp *hubp21 = TO_DCN21_HUBP(hubp);

	struct dc_debug_options *debug = &hubp->ctx->dc->debug;



	//program flip type

	REG_UPDATE(DCSURF_FLIP_CONTROL,

			SURFACE_FLIP_TYPE, flip_immediate);



	// Program VMID reg

	REG_UPDATE(VMID_SETTINGS_0,

			VMID, address->vmid);



	if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {

		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);

		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);



	} else {

		// turn off stereo if not in stereo

		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);

		REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);

	}







	/* HW automatically latch rest of address register on write to

	 * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used

	 *

	 * program high first and then the low addr, order matters!

	 */

	switch (address->type) {

	case PLN_ADDR_TYPE_GRAPHICS:

		/* DCN1.0 does not support const color

		 * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1

		 * base on address->grph.dcc_const_color

		 * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma

		 * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma

		 */



		if (address->grph.addr.quad_part == 0)

			break;



		REG_UPDATE_2(DCSURF_SURFACE_CONTROL,

				PRIMARY_SURFACE_TMZ, address->tmz_surface,

				PRIMARY_META_SURFACE_TMZ, address->tmz_surface);



		if (address->grph.meta_addr.quad_part != 0) {

			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

					PRIMARY_META_SURFACE_ADDRESS_HIGH,

					address->grph.meta_addr.high_part);



			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

					PRIMARY_META_SURFACE_ADDRESS,

					address->grph.meta_addr.low_part);

		}



		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

				PRIMARY_SURFACE_ADDRESS_HIGH,

				address->grph.addr.high_part);



		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

				PRIMARY_SURFACE_ADDRESS,

				address->grph.addr.low_part);

		break;

	case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:

		if (address->video_progressive.luma_addr.quad_part == 0

				|| address->video_progressive.chroma_addr.quad_part == 0)

			break;



		REG_UPDATE_4(DCSURF_SURFACE_CONTROL,

				PRIMARY_SURFACE_TMZ, address->tmz_surface,

				PRIMARY_SURFACE_TMZ_C, address->tmz_surface,

				PRIMARY_META_SURFACE_TMZ, address->tmz_surface,

				PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);



		if (address->video_progressive.luma_meta_addr.quad_part != 0) {

			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,

					PRIMARY_META_SURFACE_ADDRESS_HIGH_C,

					address->video_progressive.chroma_meta_addr.high_part);



			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,

					PRIMARY_META_SURFACE_ADDRESS_C,

					address->video_progressive.chroma_meta_addr.low_part);



			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

					PRIMARY_META_SURFACE_ADDRESS_HIGH,

					address->video_progressive.luma_meta_addr.high_part);



			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

					PRIMARY_META_SURFACE_ADDRESS,

					address->video_progressive.luma_meta_addr.low_part);

		}



		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,

				PRIMARY_SURFACE_ADDRESS_HIGH_C,

				address->video_progressive.chroma_addr.high_part);



		if (debug->nv12_iflip_vm_wa) {

			REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

					PRIMARY_SURFACE_ADDRESS_C,

					address->video_progressive.chroma_addr.low_part + hubp21->PLAT_54186_wa_chroma_addr_offset);

		} else {

			REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,

					PRIMARY_SURFACE_ADDRESS_C,

					address->video_progressive.chroma_addr.low_part);

		}



		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

				PRIMARY_SURFACE_ADDRESS_HIGH,

				address->video_progressive.luma_addr.high_part);



		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

				PRIMARY_SURFACE_ADDRESS,

				address->video_progressive.luma_addr.low_part);

		break;

	case PLN_ADDR_TYPE_GRPH_STEREO:

		if (address->grph_stereo.left_addr.quad_part == 0)

			break;

		if (address->grph_stereo.right_addr.quad_part == 0)

			break;



		REG_UPDATE_8(DCSURF_SURFACE_CONTROL,

				PRIMARY_SURFACE_TMZ, address->tmz_surface,

				PRIMARY_SURFACE_TMZ_C, address->tmz_surface,

				PRIMARY_META_SURFACE_TMZ, address->tmz_surface,

				PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,

				SECONDARY_SURFACE_TMZ, address->tmz_surface,

				SECONDARY_SURFACE_TMZ_C, address->tmz_surface,

				SECONDARY_META_SURFACE_TMZ, address->tmz_surface,

				SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);



		if (address->grph_stereo.right_meta_addr.quad_part != 0) {



			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,

					SECONDARY_META_SURFACE_ADDRESS_HIGH,

					address->grph_stereo.right_meta_addr.high_part);



			REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,

					SECONDARY_META_SURFACE_ADDRESS,

					address->grph_stereo.right_meta_addr.low_part);

		}

		if (address->grph_stereo.left_meta_addr.quad_part != 0) {



			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,

					PRIMARY_META_SURFACE_ADDRESS_HIGH,

					address->grph_stereo.left_meta_addr.high_part);



			REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,

					PRIMARY_META_SURFACE_ADDRESS,

					address->grph_stereo.left_meta_addr.low_part);

		}



		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,

				SECONDARY_SURFACE_ADDRESS_HIGH,

				address->grph_stereo.right_addr.high_part);



		REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,

				SECONDARY_SURFACE_ADDRESS,

				address->grph_stereo.right_addr.low_part);



		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,

				PRIMARY_SURFACE_ADDRESS_HIGH,

				address->grph_stereo.left_addr.high_part);



		REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,

				PRIMARY_SURFACE_ADDRESS,

				address->grph_stereo.left_addr.low_part);

		break;

	default:

		BREAK_TO_DEBUGGER();

		break;

	}



	hubp->request_address = *address;



	return true;

}



void hubp21_init(struct hubp *hubp)

{

	// DEDCN21-133: Inconsistent row starting line for flip between DPTE and Meta
@@ -614,7 +871,7 @@ void hubp21_init(struct hubp *hubp) 
static struct hubp_funcs dcn21_hubp_funcs = {

	.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,

	.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,

	.hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,

	.hubp_program_surface_flip_and_addr = hubp21_program_surface_flip_and_addr,

	.hubp_program_surface_config = hubp1_program_surface_config,

	.hubp_is_flip_pending = hubp1_is_flip_pending,

	.hubp_setup = hubp21_setup,
@@ -623,6 +880,7 @@ static struct hubp_funcs dcn21_hubp_funcs = { 
	.set_blank = hubp1_set_blank,

	.dcc_control = hubp1_dcc_control,

	.mem_program_viewport = hubp21_set_viewport,

	.apply_PLAT_54186_wa = hubp21_apply_PLAT_54186_wa,

	.set_cursor_attributes	= hubp2_cursor_set_attributes,

	.set_cursor_position	= hubp1_cursor_set_position,

	.hubp_clk_cntl = hubp1_clk_cntl,