Commit cf1694f0 authored by Chandramohan Akula's avatar Chandramohan Akula Committed by Jason Gunthorpe
Browse files

bnxt_en: Update HW interface headers 

Updating the HW structures for the doorbell pacing related
information. Newly added interface structures will be used in
the followup patches.

Link: https://lore.kernel.org/r/1689742977-9128-2-git-send-email-selvin.xavier@broadcom.com


CC: Michael Chan <michael.chan@broadcom.com>
Signed-off-by: default avatarChandramohan Akula <chandramohan.akula@broadcom.com>
Signed-off-by: default avatarSelvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@nvidia.com>
parent f8ef1be8

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

+54 −0
Original line number Diff line number Diff line
@@ -3721,6 +3721,60 @@ struct hwrm_func_backing_store_qcaps_v2_output { 
	u8	valid;

};



/* hwrm_func_dbr_pacing_qcfg_input (size:128b/16B) */

struct hwrm_func_dbr_pacing_qcfg_input {

	__le16  req_type;

	__le16  cmpl_ring;

	__le16  seq_id;

	__le16  target_id;

	__le64  resp_addr;

};



/* hwrm_func_dbr_pacing_qcfg_output (size:512b/64B) */

struct hwrm_func_dbr_pacing_qcfg_output {

	__le16  error_code;

	__le16  req_type;

	__le16  seq_id;

	__le16  resp_len;

	u8      flags;

#define FUNC_DBR_PACING_QCFG_RESP_FLAGS_DBR_NQ_EVENT_ENABLED     0x1UL

	u8      unused_0[7];

	__le32  dbr_stat_db_fifo_reg;

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_MASK    0x3UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_SFT     0

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_PCIE_CFG  0x0UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_GRC       0x1UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR0      0x2UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1      0x3UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_LAST     \

		FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SPACE_BAR1

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_MASK          0xfffffffcUL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_STAT_DB_FIFO_REG_ADDR_SFT           2

	__le32  dbr_stat_db_fifo_reg_watermark_mask;

	u8      dbr_stat_db_fifo_reg_watermark_shift;

	u8      unused_1[3];

	__le32  dbr_stat_db_fifo_reg_fifo_room_mask;

	u8      dbr_stat_db_fifo_reg_fifo_room_shift;

	u8      unused_2[3];

	__le32  dbr_throttling_aeq_arm_reg;

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_MASK    0x3UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_SFT     0

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_PCIE_CFG  0x0UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_GRC       0x1UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR0      0x2UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1      0x3UL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_LAST	\

		FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SPACE_BAR1

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_MASK          0xfffffffcUL

#define FUNC_DBR_PACING_QCFG_RESP_DBR_THROTTLING_AEQ_ARM_REG_ADDR_SFT           2

	u8      dbr_throttling_aeq_arm_reg_val;

	u8      unused_3[7];

	__le32  primary_nq_id;

	__le32  pacing_threshold;

	u8      unused_4[7];

	u8      valid;

};



/* hwrm_func_drv_if_change_input (size:192b/24B) */

struct hwrm_func_drv_if_change_input {

	__le16	req_type;