Loading drivers/net/phy/meson-gxl.c +36 −1 Original line number Diff line number Diff line Loading @@ -33,6 +33,14 @@ #define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0) #define TSTREAD1 21 #define TSTWRITE 23 #define INTSRC_FLAG 29 #define INTSRC_ANEG_PR BIT(1) #define INTSRC_PARALLEL_FAULT BIT(2) #define INTSRC_ANEG_LP_ACK BIT(3) #define INTSRC_LINK_DOWN BIT(4) #define INTSRC_REMOTE_FAULT BIT(5) #define INTSRC_ANEG_COMPLETE BIT(6) #define INTSRC_MASK 30 #define BANK_ANALOG_DSP 0 #define BANK_WOL 1 Loading Loading @@ -193,16 +201,43 @@ static int meson_gxl_read_status(struct phy_device *phydev) return genphy_read_status(phydev); } static int meson_gxl_ack_interrupt(struct phy_device *phydev) { int ret = phy_read(phydev, INTSRC_FLAG); return ret < 0 ? ret : 0; } static int meson_gxl_config_intr(struct phy_device *phydev) { u16 val; if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { val = INTSRC_ANEG_PR | INTSRC_PARALLEL_FAULT | INTSRC_ANEG_LP_ACK | INTSRC_LINK_DOWN | INTSRC_REMOTE_FAULT | INTSRC_ANEG_COMPLETE; } else { val = 0; } return phy_write(phydev, INTSRC_MASK, val); } static struct phy_driver meson_gxl_phy[] = { { .phy_id = 0x01814400, .phy_id_mask = 0xfffffff0, .name = "Meson GXL Internal PHY", .features = PHY_BASIC_FEATURES, .flags = PHY_IS_INTERNAL, .flags = PHY_IS_INTERNAL | PHY_HAS_INTERRUPT, .config_init = meson_gxl_config_init, .aneg_done = genphy_aneg_done, .read_status = meson_gxl_read_status, .ack_interrupt = meson_gxl_ack_interrupt, .config_intr = meson_gxl_config_intr, .suspend = genphy_suspend, .resume = genphy_resume, }, Loading Loading
drivers/net/phy/meson-gxl.c +36 −1 Original line number Diff line number Diff line Loading @@ -33,6 +33,14 @@ #define TSTCNTL_WRITE_ADDRESS GENMASK(4, 0) #define TSTREAD1 21 #define TSTWRITE 23 #define INTSRC_FLAG 29 #define INTSRC_ANEG_PR BIT(1) #define INTSRC_PARALLEL_FAULT BIT(2) #define INTSRC_ANEG_LP_ACK BIT(3) #define INTSRC_LINK_DOWN BIT(4) #define INTSRC_REMOTE_FAULT BIT(5) #define INTSRC_ANEG_COMPLETE BIT(6) #define INTSRC_MASK 30 #define BANK_ANALOG_DSP 0 #define BANK_WOL 1 Loading Loading @@ -193,16 +201,43 @@ static int meson_gxl_read_status(struct phy_device *phydev) return genphy_read_status(phydev); } static int meson_gxl_ack_interrupt(struct phy_device *phydev) { int ret = phy_read(phydev, INTSRC_FLAG); return ret < 0 ? ret : 0; } static int meson_gxl_config_intr(struct phy_device *phydev) { u16 val; if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { val = INTSRC_ANEG_PR | INTSRC_PARALLEL_FAULT | INTSRC_ANEG_LP_ACK | INTSRC_LINK_DOWN | INTSRC_REMOTE_FAULT | INTSRC_ANEG_COMPLETE; } else { val = 0; } return phy_write(phydev, INTSRC_MASK, val); } static struct phy_driver meson_gxl_phy[] = { { .phy_id = 0x01814400, .phy_id_mask = 0xfffffff0, .name = "Meson GXL Internal PHY", .features = PHY_BASIC_FEATURES, .flags = PHY_IS_INTERNAL, .flags = PHY_IS_INTERNAL | PHY_HAS_INTERRUPT, .config_init = meson_gxl_config_init, .aneg_done = genphy_aneg_done, .read_status = meson_gxl_read_status, .ack_interrupt = meson_gxl_ack_interrupt, .config_intr = meson_gxl_config_intr, .suspend = genphy_suspend, .resume = genphy_resume, }, Loading