Commit cf034628 authored by Pu Wen's avatar Pu Wen
Browse files

EDAC/amd64: Add support for Hygon family 18h model 5h 

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I7DX6V


CVE: NA

---------------------------

Hygon family 18h model 5h processor has the same F0/F6 device IDs as
F17h_M30h, and the syndrome size is the same as model 4h processor.

Signed-off-by: default avatarPu Wen <puwen@hygon.cn>
parent feb4e4c6

drivers/edac/amd64_edac.c

+8 −1
Original line number Diff line number Diff line
@@ -2854,7 +2854,8 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt) 
			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {

				if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON &&

				    boot_cpu_data.x86 == 0x18 &&

				    boot_cpu_data.x86_model == 0x4 &&

				    (boot_cpu_data.x86_model == 0x4 ||

				     boot_cpu_data.x86_model == 0x5) &&

				    (pvt->umc[i].umc_cfg & GENMASK(2, 0)) == 0x1) {

					determine_ecc_sym_sz_f18h_m4h(pvt, i);

					return;
@@ -3531,6 +3532,12 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) 
			family_types[F17_M30H_CPUS].max_mcs = 3;

			family_types[F17_M30H_CPUS].ctl_name = "F18h_M04h";

			break;

		} else if (pvt->model == 0x5) {

			fam_type = &family_types[F17_M30H_CPUS];

			pvt->ops = &family_types[F17_M30H_CPUS].ops;

			family_types[F17_M30H_CPUS].max_mcs = 1;

			family_types[F17_M30H_CPUS].ctl_name = "F18h_M05h";

			break;

		}

		fam_type	= &family_types[F17_CPUS];

		pvt->ops	= &family_types[F17_CPUS].ops;