Commit cef8cdc0 authored by Claudiu Beznea's avatar Claudiu Beznea
Browse files

ARM: at91: pm: avoid soft resetting AC DLL 



Do not soft reset AC DLL as controller is buggy and this operation my
introduce glitches in the controller leading to undefined behavior.

Fixes: f0bbf179 ("ARM: at91: pm: add self-refresh support for sama7g5")
Depends-on: a02875c4 ("ARM: at91: pm: fix self-refresh for sama7g5")
Signed-off-by: default avatarClaudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20221026124114.985876-2-claudiu.beznea@microchip.com
parent 0873509e

arch/arm/mach-at91/pm_suspend.S

+6 −1
Original line number Diff line number Diff line
@@ -169,10 +169,15 @@ sr_ena_2: 
	cmp	tmp1, #UDDRC_STAT_SELFREF_TYPE_SW

	bne	sr_ena_2



	/* Put DDR PHY's DLL in bypass mode for non-backup modes. */

	/* Disable DX DLLs for non-backup modes. */

	cmp	r7, #AT91_PM_BACKUP

	beq	sr_ena_3



	/* Do not soft reset the AC DLL. */

	ldr	tmp1, [r3, DDR3PHY_ACDLLCR]

	bic	tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST

	str	tmp1, [r3, DDR3PHY_ACDLLCR]



	/* Disable DX DLLs. */

	ldr	tmp1, [r3, #DDR3PHY_DX0DLLCR]

	orr	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS

include/soc/at91/sama7-ddr.h

+4 −1
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ 
#define	DDR3PHY_PGSR				(0x0C)		/* DDR3PHY PHY General Status Register */

#define		DDR3PHY_PGSR_IDONE		(1 << 0)	/* Initialization Done */



#define	DDR3PHY_ACDLLCR				(0x14)		/* DDR3PHY AC DLL Control Register */

#define		DDR3PHY_ACDLLCR_DLLSRST		(1 << 30)	/* DLL Soft Reset */



#define DDR3PHY_ACIOCR				(0x24)		/* DDR3PHY AC I/O Configuration Register */

#define		DDR3PHY_ACIOCR_CSPDD_CS0	(1 << 18)	/* CS#[0] Power Down Driver */

#define		DDR3PHY_ACIOCR_CKPDD_CK0	(1 << 8)	/* CK[0] Power Down Driver */