Commit cef37c78 authored by Bo Jiao's avatar Bo Jiao Committed by Felix Fietkau
Browse files

mt76: mt7915: Fix channel state update error issue 



Fix channel state update error issue due to wrong
register access for mt7916.

Signed-off-by: default avatarSujuan Chen <sujuan.chen@mediatek.com>
Signed-off-by: default avatarBo Jiao <Bo.Jiao@mediatek.com>
Signed-off-by: default avatarFelix Fietkau <nbd@nbd.name>
parent d0c0cefb

drivers/net/wireless/mediatek/mt76/mt7915/mac.c

+11 −4
Original line number Diff line number Diff line
@@ -1861,12 +1861,17 @@ void mt7915_mac_set_timing(struct mt7915_phy *phy) 


void mt7915_mac_enable_nf(struct mt7915_dev *dev, bool ext_phy)

{

	mt76_set(dev, MT_WF_PHY_RXTD12(ext_phy),

	u32 reg;



	reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RXTD12(ext_phy) :

		MT_WF_PHY_RXTD12_MT7916(ext_phy);

	mt76_set(dev, reg,

		 MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY |

		 MT_WF_PHY_RXTD12_IRPI_SW_CLR);



	mt76_set(dev, MT_WF_PHY_RX_CTRL1(ext_phy),

		 FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5));

	reg = is_mt7915(&dev->mt76) ? MT_WF_PHY_RX_CTRL1(ext_phy) :

		MT_WF_PHY_RX_CTRL1_MT7916(ext_phy);

	mt76_set(dev, reg, FIELD_PREP(MT_WF_PHY_RX_CTRL1_IPI_EN, 0x5));

}



static u8
@@ -1878,7 +1883,9 @@ mt7915_phy_get_nf(struct mt7915_phy *phy, int idx) 
	int nss, i;



	for (nss = 0; nss < hweight8(phy->mt76->chainmask); nss++) {

		u32 reg = MT_WF_IRPI(nss + (idx << dev->dbdc_support));

		u32 reg = is_mt7915(&dev->mt76) ?

			MT_WF_IRPI_NSS(0, nss + (idx << dev->dbdc_support)) :

			MT_WF_IRPI_NSS_MT7916(idx, nss);



		for (i = 0; i < ARRAY_SIZE(nf_power); i++, reg += 4) {

			val = mt76_rr(dev, reg);

drivers/net/wireless/mediatek/mt76/mt7915/mcu.c

+5 −3
Original line number Diff line number Diff line
@@ -3064,10 +3064,12 @@ int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch) 
	struct mt7915_dev *dev = phy->dev;

	struct mt7915_mcu_mib *res, req[4];

	struct sk_buff *skb;

	int i, ret, start = 0;

	int i, ret, start = 0, ofs = 20;



	if (!is_mt7915(&dev->mt76))

	if (!is_mt7915(&dev->mt76)) {

		start = 4;

		ofs = 0;

	}



	for (i = 0; i < 4; i++) {

		req[i].band = cpu_to_le32(phy != &dev->phy);
@@ -3079,7 +3081,7 @@ int mt7915_mcu_get_chan_mib_info(struct mt7915_phy *phy, bool chan_switch) 
	if (ret)

		return ret;



	res = (struct mt7915_mcu_mib *)(skb->data + 20);

	res = (struct mt7915_mcu_mib *)(skb->data + ofs);



	if (chan_switch)

		goto out;

drivers/net/wireless/mediatek/mt76/mt7915/regs.h

+8 −3
Original line number Diff line number Diff line
@@ -761,18 +761,23 @@ enum offs_rev { 
#define MT_WF_PP_TOP_RXQ_WFDMA_CF_5	MT_WF_PP_TOP(0x0e8)

#define MT_WF_PP_TOP_RXQ_QID6_WFDMA_HIF_SEL_MASK	BIT(6)



#define MT_WF_IRPI_BASE			0x83006000

#define MT_WF_IRPI(ofs)			(MT_WF_IRPI_BASE + ((ofs) << 16))

#define MT_WF_IRPI_BASE			0x83000000

#define MT_WF_IRPI(ofs)			(MT_WF_IRPI_BASE + (ofs))



/* PHY: band 0(0x83080000), band 1(0x83090000) */

#define MT_WF_IRPI_NSS(phy, nss)	MT_WF_IRPI(0x6000 + ((phy) << 20) + ((nss) << 16))

#define MT_WF_IRPI_NSS_MT7916(phy, nss)	MT_WF_IRPI(0x1000 + ((phy) << 20) + ((nss) << 16))



/* PHY */

#define MT_WF_PHY_BASE			0x83080000

#define MT_WF_PHY(ofs)			(MT_WF_PHY_BASE + (ofs))



#define MT_WF_PHY_RX_CTRL1(_phy)	MT_WF_PHY(0x2004 + ((_phy) << 16))

#define MT_WF_PHY_RX_CTRL1_MT7916(_phy)	MT_WF_PHY(0x2004 + ((_phy) << 20))

#define MT_WF_PHY_RX_CTRL1_IPI_EN	GENMASK(2, 0)

#define MT_WF_PHY_RX_CTRL1_STSCNT_EN	GENMASK(11, 9)



#define MT_WF_PHY_RXTD12(_phy)		MT_WF_PHY(0x8230 + ((_phy) << 16))

#define MT_WF_PHY_RXTD12_MT7916(_phy)	MT_WF_PHY(0x8230 + ((_phy) << 20))

#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY	BIT(18)

#define MT_WF_PHY_RXTD12_IRPI_SW_CLR		BIT(29)