Commit cecdce9d authored by Yong Wu's avatar Yong Wu Committed by Joerg Roedel
Browse files

iommu/mediatek: Use a struct as the platform data 



Use a struct as the platform special data instead of the enumeration.
This is a prepare patch for adding mt8183 iommu support.

Signed-off-by: default avatarYong Wu <yong.wu@mediatek.com>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: default avatarEvan Green <evgreen@chromium.org>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 29746d01

drivers/iommu/mtk_iommu.c

+16 −8
Original line number Original line Diff line number Diff line
@@ -46,7 +46,7 @@ 
#define REG_MMU_CTRL_REG			0x110

#define REG_MMU_CTRL_REG			0x110

#define F_MMU_PREFETCH_RT_REPLACE_MOD		BIT(4)

#define F_MMU_PREFETCH_RT_REPLACE_MOD		BIT(4)

#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \

#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \

	((data)->m4u_plat == M4U_MT2712 ? 4 : 5)

	((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)

/* It's named by F_MMU_TF_PROT_SEL in mt2712. */

/* It's named by F_MMU_TF_PROT_SEL in mt2712. */

#define F_MMU_TF_PROTECT_SEL(prot, data) \

#define F_MMU_TF_PROTECT_SEL(prot, data) \

	(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))

	(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -512,7 +512,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 
	}

	}





	regval = F_MMU_TF_PROTECT_SEL(2, data);

	regval = F_MMU_TF_PROTECT_SEL(2, data);

	if (data->m4u_plat == M4U_MT8173)

	if (data->plat_data->m4u_plat == M4U_MT8173)

		regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;

		regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;

	writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);

	writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -533,14 +533,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 
		F_INT_PRETETCH_TRANSATION_FIFO_FAULT;

		F_INT_PRETETCH_TRANSATION_FIFO_FAULT;

	writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);

	writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);





	if (data->m4u_plat == M4U_MT8173)

	if (data->plat_data->m4u_plat == M4U_MT8173)

		regval = (data->protect_base >> 1) | (data->enable_4GB << 31);

		regval = (data->protect_base >> 1) | (data->enable_4GB << 31);

	else

	else

		regval = lower_32_bits(data->protect_base) |

		regval = lower_32_bits(data->protect_base) |

			 upper_32_bits(data->protect_base);

			 upper_32_bits(data->protect_base);

	writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);

	writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);





	if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {

	if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {

		/*

		/*

		 * If 4GB mode is enabled, the validate PA range is from

		 * If 4GB mode is enabled, the validate PA range is from

		 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].

		 * 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -551,7 +551,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data) 
	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);

	writel_relaxed(0, data->base + REG_MMU_DCM_DIS);





	/* It's MISC control register whose default value is ok except mt8173.*/

	/* It's MISC control register whose default value is ok except mt8173.*/

	if (data->m4u_plat == M4U_MT8173)

	if (data->plat_data->m4u_plat == M4U_MT8173)

		writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);

		writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);





	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,

	if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -584,7 +584,7 @@ static int mtk_iommu_probe(struct platform_device *pdev) 
	if (!data)

	if (!data)

		return -ENOMEM;

		return -ENOMEM;

	data->dev = dev;

	data->dev = dev;

	data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev);

	data->plat_data = of_device_get_match_data(dev);





	/* Protect memory. HW will access here while translation fault.*/

	/* Protect memory. HW will access here while translation fault.*/

	protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);

	protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
@@ -732,9 +732,17 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = { 
	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)

	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)

};

};





static const struct mtk_iommu_plat_data mt2712_data = {

	.m4u_plat     = M4U_MT2712,

};



static const struct mtk_iommu_plat_data mt8173_data = {

	.m4u_plat     = M4U_MT8173,

};



static const struct of_device_id mtk_iommu_of_ids[] = {

static const struct of_device_id mtk_iommu_of_ids[] = {

	{ .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712},

	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},

	{ .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173},

	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},

	{}

	{}

};

};

drivers/iommu/mtk_iommu.h

+5 −1
Original line number Original line Diff line number Diff line
@@ -32,6 +32,10 @@ enum mtk_iommu_plat { 
	M4U_MT8173,

	M4U_MT8173,

};

};





struct mtk_iommu_plat_data {

	enum mtk_iommu_plat m4u_plat;

};



struct mtk_iommu_domain;

struct mtk_iommu_domain;





struct mtk_iommu_data {

struct mtk_iommu_data {
@@ -48,7 +52,7 @@ struct mtk_iommu_data { 
	bool				tlb_flush_active;

	bool				tlb_flush_active;





	struct iommu_device		iommu;

	struct iommu_device		iommu;

	enum mtk_iommu_plat		m4u_plat;

	const struct mtk_iommu_plat_data *plat_data;





	struct list_head		list;

	struct list_head		list;

};

};