Commit ceb4c8b3 authored by Chanho Park's avatar Chanho Park Committed by Sylwester Nawrocki
Browse files

clk: samsung: exynosautov9: add cmu_peris clock support 



CMU_PERIS is responsible to control clocks of BLK_PERIS which has
OPT/MCT/WDT and TMU. This patch only supports WDT gate clocks and all
other clocks except WDT will be supported later.

Signed-off-by: default avatarChanho Park <chanho61.park@samsung.com>
Signed-off-by: default avatarSylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-6-chanho61.park@samsung.com
parent 17f7dc48

drivers/clk/samsung/clk-exynosautov9.c

+51 −0
Original line number Diff line number Diff line
@@ -1015,6 +1015,53 @@ static const struct samsung_cmu_info core_cmu_info __initconst = { 
	.clk_name		= "dout_clkcmu_core_bus",

};



/* ---- CMU_PERIS ---------------------------------------------------------- */



/* Register Offset definitions for CMU_PERIS (0x10020000) */

#define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER	0x0600

#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK	0x2058

#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK	0x205c

#define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK	0x2060



static const unsigned long peris_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER,

	CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,

};



/* List of parent clocks for Muxes in CMU_PERIS */

PNAME(mout_peris_bus_user_p) = { "oscclk", "dout_clkcmu_peris_bus" };



static const struct samsung_mux_clock peris_mux_clks[] __initconst = {

	MUX(CLK_MOUT_PERIS_BUS_USER, "mout_peris_bus_user",

	    mout_peris_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER, 4, 1),

};



static const struct samsung_gate_clock peris_gate_clks[] __initconst = {

	GATE(CLK_GOUT_SYSREG_PERIS_PCLK, "gout_sysreg_peris_pclk",

	     "mout_peris_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK,

	     21, CLK_IGNORE_UNUSED, 0),

	GATE(CLK_GOUT_WDT_CLUSTER0, "gout_wdt_cluster0", "mout_peris_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,

	     21, 0, 0),

	GATE(CLK_GOUT_WDT_CLUSTER1, "gout_wdt_cluster1", "mout_peris_bus_user",

	     CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,

	     21, 0, 0),

};



static const struct samsung_cmu_info peris_cmu_info __initconst = {

	.mux_clks		= peris_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(peris_mux_clks),

	.gate_clks		= peris_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(peris_gate_clks),

	.nr_clk_ids		= PERIS_NR_CLK,

	.clk_regs		= peris_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(peris_clk_regs),

	.clk_name		= "dout_clkcmu_peris_bus",

};



static int __init exynosautov9_cmu_probe(struct platform_device *pdev)

{

	const struct samsung_cmu_info *info;
@@ -1031,6 +1078,10 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = { 
		.compatible = "samsung,exynosautov9-cmu-core",

		.data = &core_cmu_info,

	}, {

	}, {

		.compatible = "samsung,exynosautov9-cmu-peris",

		.data = &peris_cmu_info,

	}, {

	},

};