Commit ce7e5a6e authored by Jiansong Chen's avatar Jiansong Chen Committed by Alex Deucher
Browse files

drm/amd/pm: enable MP0 DPM for sienna_cichlid 



Enable MP0 clock DPM for sienna_cichlid.

Signed-off-by: default avatarJiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4cd2a96d

drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

+3 −1
Original line number Original line Diff line number Diff line
@@ -68,7 +68,8 @@ 
	FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \

	FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \

	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \

	FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \

	FEATURE_MASK(FEATURE_DPM_FCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_FCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))

	FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)	 | \

	FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))





#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15

#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
@@ -230,6 +231,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu, 




	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)

	*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)

				| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)

				| FEATURE_MASK(FEATURE_DPM_FCLK_BIT)

				| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)

				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_FCLK_BIT)

				| FEATURE_MASK(FEATURE_DS_FCLK_BIT)