Commit ce45dff1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.3-tag1' of... 

Merge tag 'renesas-clk-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add PWM, Compare-Match Timer (TIM), USB, SDHI, and eMMC clocks and
   resets on RZ/V2M
 - Add display clocks on R-Car V4H
 - Add Camera Receiving Unit (CRU) clocks and resets on RZ/G2L
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.3-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: cpg-mssr: Fix use after free if cpg_mssr_common_init() failed
  clk: renesas: r9a07g044: Add clock and reset entries for CRU
  clk: renesas: r9a09g011: Add SDHI/eMMC clock and reset entries
  clk: renesas: r9a09g011: Add USB clock and reset entries
  clk: renesas: r9a09g011: Add TIM clock and reset entries
  clk: renesas: r8a779g0: Add display related clocks
  clk: renesas: rcar-gen4: Restore PLL enum sort order
  clk: renesas: r8a779g0: Fix OSC predividers
  clk: renesas: r9a09g011: Add PWM clock and reset entries
parents 1b929c02 fbfd614a

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+13 −4
Original line number Diff line number Diff line
@@ -145,6 +145,8 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("viobusd2",	R8A779G0_CLK_VIOBUSD2,	CLK_VIO,	2, 1),

	DEF_FIXED("vcbus",	R8A779G0_CLK_VCBUS,	CLK_VC,		1, 1),

	DEF_FIXED("vcbusd2",	R8A779G0_CLK_VCBUSD2,	CLK_VC,		2, 1),

	DEF_FIXED("dsiref",	R8A779G0_CLK_DSIREF,	CLK_PLL5_DIV4,	48, 1),

	DEF_DIV6P1("dsiext",	R8A779G0_CLK_DSIEXT,	CLK_PLL5_DIV4,	0x884),



	DEF_GEN4_SDH("sd0h",	R8A779G0_CLK_SD0H,	CLK_SDSRC,	   0x870),

	DEF_GEN4_SD("sd0",	R8A779G0_CLK_SD0,	R8A779G0_CLK_SD0H, 0x870),
@@ -161,6 +163,11 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("avb0",		211,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("dis0",		411,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("dsitxlink0",	415,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("dsitxlink1",	416,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("fcpvd0",	508,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("fcpvd1",	509,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("hscif0",	514,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif1",	515,	R8A779G0_CLK_SASYNCPERD1),

	DEF_MOD("hscif2",	516,	R8A779G0_CLK_SASYNCPERD1),
@@ -193,6 +200,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("tmu3",		716,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tmu4",		717,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("tpu0",		718,	R8A779G0_CLK_SASYNCPERD4),

	DEF_MOD("vspd0",	830,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("vspd1",	831,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("wdt1:wdt0",	907,	R8A779G0_CLK_R),

	DEF_MOD("cmt0",		910,	R8A779G0_CLK_R),

	DEF_MOD("cmt1",		911,	R8A779G0_CLK_R),
@@ -211,20 +220,20 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
 *   MD	 EXTAL		PLL1	PLL2	PLL3	PLL4	PLL5	PLL6	OSC

 * 14 13 (MHz)

 * ------------------------------------------------------------------------

 * 0  0	 16.66 / 1	x192	x204	x192	x144	x192	x168	/15

 * 0  0	 16.66 / 1	x192	x204	x192	x144	x192	x168	/16

 * 0  1	 20    / 1	x160	x170	x160	x120	x160	x140	/19

 * 1  0	 Prohibited setting

 * 1  1	 33.33 / 2	x192	x204	x192	x144	x192	x168	/38

 * 1  1	 33.33 / 2	x192	x204	x192	x144	x192	x168	/32

 */

#define CPG_PLL_CONFIG_INDEX(md)	((((md) & BIT(14)) >> 13) | \

					 (((md) & BIT(13)) >> 13))



static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] = {

	/* EXTAL div	PLL1 mult/div	PLL2 mult/div	PLL3 mult/div	PLL4 mult/div	PLL5 mult/div	PLL6 mult/div	OSC prediv */

	{ 1,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	15,	},

	{ 1,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	16,	},

	{ 1,		160,	1,	170,	1,	160,	1,	120,	1,	160,	1,	140,	1,	19,	},

	{ 0,		0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	0,	},

	{ 2,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	38,	},

	{ 2,		192,	1,	204,	1,	192,	1,	144,	1,	192,	1,	168,	1,	32,	},

};



static int __init r8a779g0_cpg_mssr_init(struct device *dev)

drivers/clk/renesas/r9a07g044-cpg.c

+25 −1
Original line number Diff line number Diff line
@@ -182,7 +182,7 @@ static const struct { 
};



static const struct {

	struct rzg2l_mod_clk common[75];

	struct rzg2l_mod_clk common[79];

#ifdef CONFIG_CLK_R9A07G054

	struct rzg2l_mod_clk drp[0];

#endif
@@ -250,6 +250,14 @@ static const struct { 
					0x558, 1),

		DEF_MOD("gpu_ace_clk",	R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,

					0x558, 2),

		DEF_MOD("cru_sysclk",   R9A07G044_CRU_SYSCLK, CLK_M2_DIV2,

					0x564, 0),

		DEF_MOD("cru_vclk",     R9A07G044_CRU_VCLK, R9A07G044_CLK_M2,

					0x564, 1),

		DEF_MOD("cru_pclk",     R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT,

					0x564, 2),

		DEF_MOD("cru_aclk",     R9A07G044_CRU_ACLK, R9A07G044_CLK_M0,

					0x564, 3),

		DEF_MOD("dsi_pll_clk",	R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,

					0x568, 0),

		DEF_MOD("dsi_sys_clk",	R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
@@ -368,6 +376,9 @@ static struct rzg2l_reset r9a07g044_resets[] = { 
	DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),

	DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),

	DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),

	DEF_RST(R9A07G044_CRU_CMN_RSTB, 0x864, 0),

	DEF_RST(R9A07G044_CRU_PRESETN, 0x864, 1),

	DEF_RST(R9A07G044_CRU_ARESETN, 0x864, 2),

	DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),

	DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),

	DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
@@ -412,6 +423,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { 
	MOD_CLK_BASE + R9A07G044_DMAC_ACLK,

};



static const unsigned int r9a07g044_no_pm_mod_clks[] = {

	MOD_CLK_BASE + R9A07G044_CRU_SYSCLK,

	MOD_CLK_BASE + R9A07G044_CRU_VCLK,

};



#ifdef CONFIG_CLK_R9A07G044

const struct rzg2l_cpg_info r9a07g044_cpg_info = {

	/* Core Clocks */
@@ -429,6 +445,10 @@ const struct rzg2l_cpg_info r9a07g044_cpg_info = { 
	.num_mod_clks = ARRAY_SIZE(mod_clks.common),

	.num_hw_mod_clks = R9A07G044_TSU_PCLK + 1,



	/* No PM Module Clocks */

	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,

	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),



	/* Resets */

	.resets = r9a07g044_resets,

	.num_resets = R9A07G044_TSU_PRESETN + 1, /* Last reset ID + 1 */
@@ -454,6 +474,10 @@ const struct rzg2l_cpg_info r9a07g054_cpg_info = { 
	.num_mod_clks = ARRAY_SIZE(mod_clks.common) + ARRAY_SIZE(mod_clks.drp),

	.num_hw_mod_clks = R9A07G054_STPAI_ACLK_DRP + 1,



	/* No PM Module Clocks */

	.no_pm_mod_clks = r9a07g044_no_pm_mod_clks,

	.num_no_pm_mod_clks = ARRAY_SIZE(r9a07g044_no_pm_mod_clks),



	/* Resets */

	.resets = r9a07g044_resets,

	.num_resets = R9A07G054_STPAI_ARESETN + 1, /* Last reset ID + 1 */

drivers/clk/renesas/r9a09g011-cpg.c

+73 −0
Original line number Diff line number Diff line
@@ -23,11 +23,14 @@ 


#define DIV_A		DDIV_PACK(0x200, 0, 3)

#define DIV_B		DDIV_PACK(0x204, 0, 2)

#define DIV_D		DDIV_PACK(0x204, 4, 2)

#define DIV_E		DDIV_PACK(0x204, 8, 1)

#define DIV_W		DDIV_PACK(0x328, 0, 3)



#define SEL_B		SEL_PLL_PACK(0x214, 0, 1)

#define SEL_D		SEL_PLL_PACK(0x214, 1, 1)

#define SEL_E		SEL_PLL_PACK(0x214, 2, 1)

#define SEL_SDI		SEL_PLL_PACK(0x300, 0, 1)

#define SEL_W0		SEL_PLL_PACK(0x32C, 0, 1)



enum clk_ids {
@@ -50,11 +53,14 @@ enum clk_ids { 
	CLK_PLL4,

	CLK_DIV_A,

	CLK_DIV_B,

	CLK_DIV_D,

	CLK_DIV_E,

	CLK_DIV_W,

	CLK_SEL_B,

	CLK_SEL_B_D2,

	CLK_SEL_D,

	CLK_SEL_E,

	CLK_SEL_SDI,

	CLK_SEL_W0,



	/* Module Clocks */
@@ -81,6 +87,14 @@ static const struct clk_div_table dtable_divb[] = { 
	{0, 0},

};



static const struct clk_div_table dtable_divd[] = {

	{0, 1},

	{1, 2},

	{2, 4},

	{0, 0},

};





static const struct clk_div_table dtable_divw[] = {

	{0, 6},

	{1, 7},
@@ -94,8 +108,10 @@ static const struct clk_div_table dtable_divw[] = { 


/* Mux clock tables */

static const char * const sel_b[] = { ".main", ".divb" };

static const char * const sel_d[] = { ".main", ".divd" };

static const char * const sel_e[] = { ".main", ".dive" };

static const char * const sel_w[] = { ".main", ".divw" };

static const char * const sel_sdi[] = { ".main", ".pll2_200" };



static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {

	/* External Clock Inputs */
@@ -115,11 +131,14 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { 


	DEF_DIV_RO(".diva",	CLK_DIV_A,	CLK_PLL1,	DIV_A,	dtable_diva),

	DEF_DIV_RO(".divb",	CLK_DIV_B,	CLK_PLL2_400,	DIV_B,	dtable_divb),

	DEF_DIV_RO(".divd",	CLK_DIV_D,	CLK_PLL2_200,	DIV_D,	dtable_divd),

	DEF_DIV_RO(".dive",	CLK_DIV_E,	CLK_PLL2_100,	DIV_E,	NULL),

	DEF_DIV_RO(".divw",	CLK_DIV_W,	CLK_PLL4,	DIV_W,	dtable_divw),



	DEF_MUX_RO(".selb",	CLK_SEL_B,	SEL_B,		sel_b),

	DEF_MUX_RO(".seld",	CLK_SEL_D,	SEL_D,		sel_d),

	DEF_MUX_RO(".sele",	CLK_SEL_E,	SEL_E,		sel_e),

	DEF_MUX(".selsdi",	CLK_SEL_SDI,	SEL_SDI,	sel_sdi),

	DEF_MUX(".selw0",	CLK_SEL_W0,	SEL_W0,		sel_w),



	DEF_FIXED(".selb_d2",	CLK_SEL_B_D2,	CLK_SEL_B,	1,	2),
@@ -128,14 +147,55 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = { 
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {

	DEF_MOD("pfc",		R9A09G011_PFC_PCLK,	 CLK_MAIN,     0x400, 2),

	DEF_MOD("gic",		R9A09G011_GIC_CLK,	 CLK_SEL_B_D2, 0x400, 5),

	DEF_MOD("sdi0_aclk",	R9A09G011_SDI0_ACLK,	 CLK_SEL_D,    0x408, 0),

	DEF_MOD("sdi0_imclk",	R9A09G011_SDI0_IMCLK,	 CLK_SEL_SDI,  0x408, 1),

	DEF_MOD("sdi0_imclk2",	R9A09G011_SDI0_IMCLK2,	 CLK_SEL_SDI,  0x408, 2),

	DEF_MOD("sdi0_clk_hs",	R9A09G011_SDI0_CLK_HS,	 CLK_PLL2_800, 0x408, 3),

	DEF_MOD("sdi1_aclk",	R9A09G011_SDI1_ACLK,	 CLK_SEL_D,    0x408, 4),

	DEF_MOD("sdi1_imclk",	R9A09G011_SDI1_IMCLK,	 CLK_SEL_SDI,  0x408, 5),

	DEF_MOD("sdi1_imclk2",	R9A09G011_SDI1_IMCLK2,	 CLK_SEL_SDI,  0x408, 6),

	DEF_MOD("sdi1_clk_hs",	R9A09G011_SDI1_CLK_HS,	 CLK_PLL2_800, 0x408, 7),

	DEF_MOD("emm_aclk",	R9A09G011_EMM_ACLK,	 CLK_SEL_D,    0x408, 8),

	DEF_MOD("emm_imclk",	R9A09G011_EMM_IMCLK,	 CLK_SEL_SDI,  0x408, 9),

	DEF_MOD("emm_imclk2",	R9A09G011_EMM_IMCLK2,	 CLK_SEL_SDI,  0x408, 10),

	DEF_MOD("emm_clk_hs",	R9A09G011_EMM_CLK_HS,	 CLK_PLL2_800, 0x408, 11),

	DEF_COUPLED("eth_axi",	R9A09G011_ETH0_CLK_AXI,	 CLK_PLL2_200, 0x40c, 8),

	DEF_COUPLED("eth_chi",	R9A09G011_ETH0_CLK_CHI,	 CLK_PLL2_100, 0x40c, 8),

	DEF_MOD("eth_clk_gptp",	R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),

	DEF_MOD("usb_aclk_h",	R9A09G011_USB_ACLK_H,	 CLK_SEL_D,    0x40c, 4),

	DEF_MOD("usb_aclk_p",	R9A09G011_USB_ACLK_P,	 CLK_SEL_D,    0x40c, 5),

	DEF_MOD("usb_pclk",	R9A09G011_USB_PCLK,	 CLK_SEL_E,    0x40c, 6),

	DEF_MOD("syc_cnt_clk",	R9A09G011_SYC_CNT_CLK,	 CLK_MAIN_24,  0x41c, 12),

	DEF_MOD("iic_pclk0",	R9A09G011_IIC_PCLK0,	 CLK_SEL_E,    0x420, 12),

	DEF_MOD("cperi_grpb",	R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E,  0x424, 0),

	DEF_MOD("tim_clk_8",	R9A09G011_TIM8_CLK,	 CLK_MAIN_2,   0x424, 4),

	DEF_MOD("tim_clk_9",	R9A09G011_TIM9_CLK,	 CLK_MAIN_2,   0x424, 5),

	DEF_MOD("tim_clk_10",	R9A09G011_TIM10_CLK,	 CLK_MAIN_2,   0x424, 6),

	DEF_MOD("tim_clk_11",	R9A09G011_TIM11_CLK,	 CLK_MAIN_2,   0x424, 7),

	DEF_MOD("tim_clk_12",	R9A09G011_TIM12_CLK,	 CLK_MAIN_2,   0x424, 8),

	DEF_MOD("tim_clk_13",	R9A09G011_TIM13_CLK,	 CLK_MAIN_2,   0x424, 9),

	DEF_MOD("tim_clk_14",	R9A09G011_TIM14_CLK,	 CLK_MAIN_2,   0x424, 10),

	DEF_MOD("tim_clk_15",	R9A09G011_TIM15_CLK,	 CLK_MAIN_2,   0x424, 11),

	DEF_MOD("iic_pclk1",	R9A09G011_IIC_PCLK1,	 CLK_SEL_E,    0x424, 12),

	DEF_MOD("cperi_grpc",	R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E,  0x428, 0),

	DEF_MOD("tim_clk_16",	R9A09G011_TIM16_CLK,	 CLK_MAIN_2,   0x428, 4),

	DEF_MOD("tim_clk_17",	R9A09G011_TIM17_CLK,	 CLK_MAIN_2,   0x428, 5),

	DEF_MOD("tim_clk_18",	R9A09G011_TIM18_CLK,	 CLK_MAIN_2,   0x428, 6),

	DEF_MOD("tim_clk_19",	R9A09G011_TIM19_CLK,	 CLK_MAIN_2,   0x428, 7),

	DEF_MOD("tim_clk_20",	R9A09G011_TIM20_CLK,	 CLK_MAIN_2,   0x428, 8),

	DEF_MOD("tim_clk_21",	R9A09G011_TIM21_CLK,	 CLK_MAIN_2,   0x428, 9),

	DEF_MOD("tim_clk_22",	R9A09G011_TIM22_CLK,	 CLK_MAIN_2,   0x428, 10),

	DEF_MOD("tim_clk_23",	R9A09G011_TIM23_CLK,	 CLK_MAIN_2,   0x428, 11),

	DEF_MOD("wdt0_pclk",	R9A09G011_WDT0_PCLK,	 CLK_SEL_E,    0x428, 12),

	DEF_MOD("wdt0_clk",	R9A09G011_WDT0_CLK,	 CLK_MAIN,     0x428, 13),

	DEF_MOD("cperi_grpf",	R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E,  0x434, 0),

	DEF_MOD("pwm8_clk",	R9A09G011_PWM8_CLK,	 CLK_MAIN,     0x434, 4),

	DEF_MOD("pwm9_clk",	R9A09G011_PWM9_CLK,	 CLK_MAIN,     0x434, 5),

	DEF_MOD("pwm10_clk",	R9A09G011_PWM10_CLK,	 CLK_MAIN,     0x434, 6),

	DEF_MOD("pwm11_clk",	R9A09G011_PWM11_CLK,	 CLK_MAIN,     0x434, 7),

	DEF_MOD("pwm12_clk",	R9A09G011_PWM12_CLK,	 CLK_MAIN,     0x434, 8),

	DEF_MOD("pwm13_clk",	R9A09G011_PWM13_CLK,	 CLK_MAIN,     0x434, 9),

	DEF_MOD("pwm14_clk",	R9A09G011_PWM14_CLK,	 CLK_MAIN,     0x434, 10),

	DEF_MOD("urt_pclk",	R9A09G011_URT_PCLK,	 CLK_SEL_E,    0x438, 4),

	DEF_MOD("urt0_clk",	R9A09G011_URT0_CLK,	 CLK_SEL_W0,   0x438, 5),

	DEF_MOD("ca53",		R9A09G011_CA53_CLK,	 CLK_DIV_A,    0x448, 0),
@@ -143,8 +203,18 @@ static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { 


static const struct rzg2l_reset r9a09g011_resets[] = {

	DEF_RST(R9A09G011_PFC_PRESETN,		0x600, 2),

	DEF_RST_MON(R9A09G011_SDI0_IXRST,	0x608, 0,  6),

	DEF_RST_MON(R9A09G011_SDI1_IXRST,	0x608, 1,  7),

	DEF_RST_MON(R9A09G011_EMM_IXRST,	0x608, 2,  8),

	DEF_RST(R9A09G011_USB_PRESET_N,		0x608, 7),

	DEF_RST(R9A09G011_USB_DRD_RESET,	0x608, 8),

	DEF_RST(R9A09G011_USB_ARESETN_P,	0x608, 9),

	DEF_RST(R9A09G011_USB_ARESETN_H,	0x608, 10),

	DEF_RST_MON(R9A09G011_ETH0_RST_HW_N,	0x608, 11, 11),

	DEF_RST_MON(R9A09G011_SYC_RST_N,	0x610, 9,  13),

	DEF_RST(R9A09G011_TIM_GPB_PRESETN,	0x614, 1),

	DEF_RST(R9A09G011_TIM_GPC_PRESETN,	0x614, 2),

	DEF_RST_MON(R9A09G011_PWM_GPF_PRESETN,	0x614, 5, 23),

	DEF_RST(R9A09G011_IIC_GPA_PRESETN,	0x614, 8),

	DEF_RST(R9A09G011_IIC_GPB_PRESETN,	0x614, 9),

	DEF_RST_MON(R9A09G011_WDT0_PRESETN,	0x614, 12, 19),
@@ -152,6 +222,9 @@ static const struct rzg2l_reset r9a09g011_resets[] = { 


static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {

	MOD_CLK_BASE + R9A09G011_CA53_CLK,

	MOD_CLK_BASE + R9A09G011_CPERI_GRPB_PCLK,

	MOD_CLK_BASE + R9A09G011_CPERI_GRPC_PCLK,

	MOD_CLK_BASE + R9A09G011_CPERI_GRPF_PCLK,

	MOD_CLK_BASE + R9A09G011_GIC_CLK,

	MOD_CLK_BASE + R9A09G011_SYC_CNT_CLK,

	MOD_CLK_BASE + R9A09G011_URT_PCLK,

drivers/clk/renesas/rcar-gen4-cpg.h

+1 −1
Original line number Diff line number Diff line
@@ -15,8 +15,8 @@ enum rcar_gen4_clk_types { 
	CLK_TYPE_GEN4_PLL2,

	CLK_TYPE_GEN4_PLL2X_3X,	/* r8a779a0 only */

	CLK_TYPE_GEN4_PLL3,

	CLK_TYPE_GEN4_PLL5,

	CLK_TYPE_GEN4_PLL4,

	CLK_TYPE_GEN4_PLL5,

	CLK_TYPE_GEN4_PLL6,

	CLK_TYPE_GEN4_SDSRC,

	CLK_TYPE_GEN4_SDH,

drivers/clk/renesas/renesas-cpg-mssr.c

+2 −1
Original line number Diff line number Diff line
@@ -989,7 +989,6 @@ static int __init cpg_mssr_common_init(struct device *dev, 
		goto out_err;

	}



	cpg_mssr_priv = priv;

	priv->num_core_clks = info->num_total_core_clks;

	priv->num_mod_clks = info->num_hw_mod_clks;

	priv->last_dt_core_clk = info->last_dt_core_clk;
@@ -1019,6 +1018,8 @@ static int __init cpg_mssr_common_init(struct device *dev, 
	if (error)

		goto out_err;



	cpg_mssr_priv = priv;



	return 0;



out_err: