Commit ce2d99a8 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/mmhub2.0: convert to IP version checking 



Use IP versions rather than asic_type to differentiate
IP version specific features.

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fac17723

drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

+32 −41
Original line number Diff line number Diff line
@@ -153,18 +153,16 @@ mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev, 
	dev_err(adev->dev,

		"MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",

		status);

	switch (adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI12:

	case CHIP_NAVI14:

	switch (adev->ip_versions[MMHUB_HWIP]) {

	case IP_VERSION(2, 0, 0):

	case IP_VERSION(2, 0, 2):

		mmhub_cid = mmhub_client_ids_navi1x[cid][rw];

		break;

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

		mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];

		break;

	case CHIP_BEIGE_GOBY:

	case IP_VERSION(2, 1, 2):

		mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];

		break;

	default:
@@ -571,11 +569,10 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
	if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))

		return;



	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	switch (adev->ip_versions[MMHUB_HWIP]) {

	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

		break;
@@ -606,11 +603,10 @@ static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *ad 
			  DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);

	}



	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	switch (adev->ip_versions[MMHUB_HWIP]) {

	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		if (def != data)

			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);

		if (def1 != data1)
@@ -633,11 +629,10 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
	if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))

		return;



	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	switch (adev->ip_versions[MMHUB_HWIP]) {

	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		break;

	default:
@@ -651,11 +646,10 @@ static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *ade 
		data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;



	if (def != data) {

		switch (adev->asic_type) {

		case CHIP_SIENNA_CICHLID:

		case CHIP_NAVY_FLOUNDER:

		case CHIP_DIMGREY_CAVEFISH:

		case CHIP_BEIGE_GOBY:

		switch (adev->ip_versions[MMHUB_HWIP]) {

		case IP_VERSION(2, 1, 0):

		case IP_VERSION(2, 1, 1):

		case IP_VERSION(2, 1, 2):

			WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);

			break;

		default:
@@ -671,14 +665,12 @@ static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev, 
	if (amdgpu_sriov_vf(adev))

		return 0;



	switch (adev->asic_type) {

	case CHIP_NAVI10:

	case CHIP_NAVI14:

	case CHIP_NAVI12:

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	switch (adev->ip_versions[MMHUB_HWIP]) {

	case IP_VERSION(2, 0, 0):

	case IP_VERSION(2, 0, 2):

	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		mmhub_v2_0_update_medium_grain_clock_gating(adev,

				state == AMD_CG_STATE_GATE);

		mmhub_v2_0_update_medium_grain_light_sleep(adev,
@@ -698,11 +690,10 @@ static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags) 
	if (amdgpu_sriov_vf(adev))

		*flags = 0;



	switch (adev->asic_type) {

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_BEIGE_GOBY:

	switch (adev->ip_versions[MMHUB_HWIP]) {

	case IP_VERSION(2, 1, 0):

	case IP_VERSION(2, 1, 1):

	case IP_VERSION(2, 1, 2):

		data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);

		data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);

		break;