Commit ce1c6623 authored by Wang Zhimin's avatar Wang Zhimin
Browse files

mm/init: Add quirk for phytium ps23064 SoC 

phytium inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/IBR7VA


CVE: NA

-------------------------------------------------------

Enabling KASAN in the Phytium ps23064 SoC will result in a reduction
in linear mapping space, leading to a failure and panic in allocating
percpu variables. This patch avoid this problem throuth removing high
physical addresses, but it should be note that device should not be
attach to die 5-7.

Signed-off-by: default avatarHuang Shaobo <huangshaobo2075@phytium.com.cn>
Signed-off-by: default avatarWang Zhimin <wangzhimin1179@phytium.com.cn>
parent 2d7a642a

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -119,6 +119,7 @@ 
#define PHYTIUM_CPU_PART_2000PLUS	0X662

#define PHYTIUM_CPU_PART_2004	        0X663

#define PHYTIUM_CPU_PART_2500		0X663

#define PHYTIUM_CPU_PART_FTC862		0x862



#define APPLE_CPU_PART_M1_ICESTORM	0x022

#define APPLE_CPU_PART_M1_FIRESTORM	0x023
@@ -170,6 +171,7 @@ 
#define MIDR_FT_2000PLUS MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2000PLUS)

#define MIDR_FT_2004     MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2004)

#define MIDR_FT_2500	 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_2500)

#define MIDR_PHYTIUM_FTC862	 MIDR_CPU_MODEL(ARM_CPU_IMP_PHYTIUM, PHYTIUM_CPU_PART_FTC862)

#define MIDR_APPLE_M1_ICESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_ICESTORM)

#define MIDR_APPLE_M1_FIRESTORM MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M1_FIRESTORM)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)

arch/arm64/mm/init.c

+17 −1
Original line number Diff line number Diff line
@@ -412,6 +412,19 @@ static int __init parse_memmap_opt(char *str) 
}

early_param("memmap", parse_memmap_opt);



#ifdef CONFIG_ARCH_PHYTIUM

#define SOCID_PS23064 0x8

#define RMV_PS23064 0x510783f00000

static inline void phytium_ps23064_quirk(void)

{

	if (read_sysreg_s(SYS_AIDR_EL1) == SOCID_PS23064 &&

		read_cpuid_id() == MIDR_PHYTIUM_FTC862) {

		pr_warn("Enable Phytium S5000C-128 Core quirk\n");

		memblock_remove(RMV_PS23064, (1ULL << PHYS_MASK_SHIFT) - RMV_PS23064);

	}

}

#endif



void __init arm64_memblock_init(void)

{

	const s64 linear_region_size = BIT(vabits_actual - 1);
@@ -421,7 +434,10 @@ void __init arm64_memblock_init(void) 


	/* Remove memory above our supported physical address size */

	memblock_remove(1ULL << PHYS_MASK_SHIFT, ULLONG_MAX);



#ifdef CONFIG_ARCH_PHYTIUM

	if (IS_ENABLED(CONFIG_KASAN))

		phytium_ps23064_quirk();

#endif

	/*

	 * Select a suitable value for the base of physical memory.

	 */