Commit ce17ce17 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
Browse files

drm/amd/display: add option to override cr training pattern 



Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 0b02e1fd

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+21 −12
Original line number Diff line number Diff line
@@ -101,7 +101,16 @@ static void dpcd_set_training_pattern( 
		dpcd_pattern.v1_4.TRAINING_PATTERN_SET);

}



static enum dc_dp_training_pattern get_supported_tp(struct dc_link *link)

static enum dc_dp_training_pattern decide_cr_training_pattern(

		const struct dc_link_settings *link_settings)

{

	enum dc_dp_training_pattern pattern = DP_TRAINING_PATTERN_SEQUENCE_1;



	return pattern;

}



static enum dc_dp_training_pattern decide_eq_training_pattern(struct dc_link *link,

		const struct dc_link_settings *link_settings)

{

	enum dc_dp_training_pattern highest_tp = DP_TRAINING_PATTERN_SEQUENCE_2;

	struct encoder_feature_support *features = &link->link_enc->features;
@@ -132,7 +141,6 @@ static void dpcd_set_link_settings( 


	union down_spread_ctrl downspread = { {0} };

	union lane_count_set lane_count_set = { {0} };

	enum dc_dp_training_pattern dp_tr_pattern;



	downspread.raw = (uint8_t)

	(lt_settings->link_settings.link_spread);
@@ -143,9 +151,8 @@ static void dpcd_set_link_settings( 
	lane_count_set.bits.ENHANCED_FRAMING = lt_settings->enhanced_framing;

	lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = 0;



	dp_tr_pattern = get_supported_tp(link);



	if (dp_tr_pattern != DP_TRAINING_PATTERN_SEQUENCE_4) {

	if (lt_settings->pattern_for_eq < DP_TRAINING_PATTERN_SEQUENCE_4) {

		lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED =

				link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;

	}
@@ -979,7 +986,7 @@ static void start_clock_recovery_pattern_early(struct dc_link *link, 
{

	DC_LOG_HW_LINK_TRAINING("%s\n GPU sends TPS1. Wait 400us.\n",

			__func__);

	dp_set_hw_training_pattern(link, DP_TRAINING_PATTERN_SEQUENCE_1, offset);

	dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);

	dp_set_hw_lane_settings(link, lt_settings, offset);

	udelay(400);

}
@@ -994,7 +1001,6 @@ static enum link_training_result perform_clock_recovery_sequence( 
	uint32_t wait_time_microsec;

	struct link_training_settings req_settings;

	enum dc_lane_count lane_count = lt_settings->link_settings.lane_count;

	enum dc_dp_training_pattern tr_pattern = DP_TRAINING_PATTERN_SEQUENCE_1;

	union lane_status dpcd_lane_status[LANE_COUNT_DP_MAX];

	union lane_align_status_updated dpcd_lane_status_updated;
@@ -1002,7 +1008,7 @@ static enum link_training_result perform_clock_recovery_sequence( 
	retry_count = 0;



	if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)

		dp_set_hw_training_pattern(link, tr_pattern, offset);

		dp_set_hw_training_pattern(link, lt_settings->pattern_for_cr, offset);



	/* najeeb - The synaptics MST hub can put the LT in

	* infinite loop by switching the VS
@@ -1029,7 +1035,7 @@ static enum link_training_result perform_clock_recovery_sequence( 
			dpcd_set_lt_pattern_and_lane_settings(

					link,

					lt_settings,

					tr_pattern,

					lt_settings->pattern_for_cr,

					offset);

		else

			dpcd_set_lane_settings(
@@ -1113,7 +1119,7 @@ static inline enum link_training_result perform_link_training_int( 
	 * TPS4 must be used instead of POST_LT_ADJ_REQ.

	 */

	if (link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED != 1 ||

			get_supported_tp(link) == DP_TRAINING_PATTERN_SEQUENCE_4)

			lt_settings->pattern_for_eq == DP_TRAINING_PATTERN_SEQUENCE_4)

		return status;



	if (status == LINK_TRAINING_SUCCESS &&
@@ -1252,10 +1258,14 @@ static void initialize_training_settings( 
	else

		lt_settings->eq_pattern_time = get_training_aux_rd_interval(link, 400);



	if (overrides->pattern_for_cr != NULL)

		lt_settings->pattern_for_cr = *overrides->pattern_for_cr;

	else

		lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);

	if (overrides->pattern_for_eq != NULL)

		lt_settings->pattern_for_eq = *overrides->pattern_for_eq;

	else

		lt_settings->pattern_for_eq = get_supported_tp(link);

		lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting);



	if (overrides->enhanced_framing != NULL)

		lt_settings->enhanced_framing = *overrides->enhanced_framing;
@@ -1457,7 +1467,6 @@ bool dc_link_dp_perform_link_training_skip_aux( 
	const struct dc_link_settings *link_setting)

{

	struct link_training_settings lt_settings;

	enum dc_dp_training_pattern pattern_for_cr = DP_TRAINING_PATTERN_SEQUENCE_1;



	initialize_training_settings(

			link,
@@ -1468,7 +1477,7 @@ bool dc_link_dp_perform_link_training_skip_aux( 
	/* 1. Perform_clock_recovery_sequence. */



	/* transmit training pattern for clock recovery */

	dp_set_hw_training_pattern(link, pattern_for_cr, DPRX);

	dp_set_hw_training_pattern(link, lt_settings.pattern_for_cr, DPRX);



	/* call HWSS to set lane settings*/

	dp_set_hw_lane_settings(link, &lt_settings, DPRX);

drivers/gpu/drm/amd/display/dc/dc_dp_types.h

+1 −0
Original line number Diff line number Diff line
@@ -123,6 +123,7 @@ struct dc_link_training_overrides { 


	uint16_t *cr_pattern_time;

	uint16_t *eq_pattern_time;

	enum dc_dp_training_pattern *pattern_for_cr;

	enum dc_dp_training_pattern *pattern_for_eq;



	enum dc_link_spread *downspread;

drivers/gpu/drm/amd/display/include/link_service_types.h

+1 −0
Original line number Diff line number Diff line
@@ -80,6 +80,7 @@ struct link_training_settings { 


	uint16_t cr_pattern_time;

	uint16_t eq_pattern_time;

	enum dc_dp_training_pattern pattern_for_cr;

	enum dc_dp_training_pattern pattern_for_eq;



	bool enhanced_framing;