Commit cdd8e16f authored by Chris Metcalf's avatar Chris Metcalf
Browse files

arch/tile: return SIGBUS for addresses that are unaligned AND invalid 



Previously we were returning SIGSEGV in this case.  It seems cleaner
to return SIGBUS since the hardware figures out alignment traps
before TLB violations, so SIGBUS is the "more correct" signal.

Signed-off-by: default avatarChris Metcalf <cmetcalf@tilera.com>
parent 54229ff3

arch/tile/kernel/single_step.c

+19 −12
Original line number Diff line number Diff line
@@ -153,6 +153,25 @@ static tile_bundle_bits rewrite_load_store_unaligned( 
	if (((unsigned long)addr % size) == 0)

		return bundle;



	/*

	 * Return SIGBUS with the unaligned address, if requested.

	 * Note that we return SIGBUS even for completely invalid addresses

	 * as long as they are in fact unaligned; this matches what the

	 * tilepro hardware would be doing, if it could provide us with the

	 * actual bad address in an SPR, which it doesn't.

	 */

	if (unaligned_fixup == 0) {

		siginfo_t info = {

			.si_signo = SIGBUS,

			.si_code = BUS_ADRALN,

			.si_addr = addr

		};

		trace_unhandled_signal("unaligned trap", regs,

				       (unsigned long)addr, SIGBUS);

		force_sig_info(info.si_signo, &info, current);

		return (tilepro_bundle_bits) 0;

	}



#ifndef __LITTLE_ENDIAN

# error We assume little-endian representation with copy_xx_user size 2 here

#endif
@@ -192,18 +211,6 @@ static tile_bundle_bits rewrite_load_store_unaligned( 
		return (tile_bundle_bits) 0;

	}



	if (unaligned_fixup == 0) {

		siginfo_t info = {

			.si_signo = SIGBUS,

			.si_code = BUS_ADRALN,

			.si_addr = addr

		};

		trace_unhandled_signal("unaligned trap", regs,

				       (unsigned long)addr, SIGBUS);

		force_sig_info(info.si_signo, &info, current);

		return (tile_bundle_bits) 0;

	}



	if (unaligned_printk || unaligned_fixup_count == 0) {

		pr_info("Process %d/%s: PC %#lx: Fixup of"

			" unaligned %s at %#lx.\n",