Commit cd951b39 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'amd-drm-next-5.13-2021-04-12' of... 

Merge tag 'amd-drm-next-5.13-2021-04-12' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-next

amd-drm-next-5.13-2021-04-12:

amdgpu:
- Re-enable GPU reset on VanGogh
- Enable DPM flags for SMART_SUSPEND and MAY_SKIP_RESUME
- Disentangle HG from vga_switcheroo
- S0ix fixes
- W=1 fixes
- Resource iterator fixes
- DMCUB updates
- UBSAN fixes
- More PM API cleanup
- Aldebaran updates
- Modifier fixes
- Enable VCN load balancing with asymmetric engines
- Rework BO structs
- Aldebaran reset support
- Initial LTTPR display work
- Display MALL fixes
- Fall back to YCbCr420 when YCbCr444 fails
- SR-IOV fixes
- RAS updates
- Misc cleanups and fixes

radeon:
- Typo fixes
- Fix error handling for firmware on r6xx
- Fix a missing check in DP MST handling

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210412220732.3845-1-alexander.deucher@amd.com
parents c103b850 cbb8f989

drivers/gpu/drm/amd/amdgpu/Makefile

+7 −2
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ amdgpu-y += \ 
	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \

	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \

	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o

	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o



# add DF block

amdgpu-y += \
@@ -88,7 +88,7 @@ amdgpu-y += \ 


# add UMC block

amdgpu-y += \

	umc_v6_1.o umc_v6_0.o umc_v8_7.o

	umc_v6_0.o umc_v6_1.o umc_v6_7.o umc_v8_7.o



# add IH block

amdgpu-y += \
@@ -179,9 +179,14 @@ amdgpu-y += \ 
	smuio_v11_0_6.o \

	smuio_v13_0.o



# add reset block

amdgpu-y += \

	amdgpu_reset.o



# add amdkfd interfaces

amdgpu-y += amdgpu_amdkfd.o





ifneq ($(CONFIG_HSA_AMD),)

AMDKFD_PATH := ../amdkfd

include $(FULL_AMD_PATH)/amdkfd/Makefile

drivers/gpu/drm/amd/amdgpu/aldebaran.c

0 → 100644
+407 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#include "aldebaran.h"

#include "amdgpu_reset.h"

#include "amdgpu_amdkfd.h"

#include "amdgpu_dpm.h"

#include "amdgpu_job.h"

#include "amdgpu_ring.h"

#include "amdgpu_ras.h"

#include "amdgpu_psp.h"

#include "amdgpu_xgmi.h"



static struct amdgpu_reset_handler *

aldebaran_get_reset_handler(struct amdgpu_reset_control *reset_ctl,

			    struct amdgpu_reset_context *reset_context)

{

	struct amdgpu_reset_handler *handler;

	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;



	if (reset_context->method != AMD_RESET_METHOD_NONE) {

		dev_dbg(adev->dev, "Getting reset handler for method %d\n",

			reset_context->method);

		list_for_each_entry(handler, &reset_ctl->reset_handlers,

				     handler_list) {

			if (handler->reset_method == reset_context->method)

				return handler;

		}

	}



	if (adev->gmc.xgmi.connected_to_cpu) {

		list_for_each_entry(handler, &reset_ctl->reset_handlers,

				     handler_list) {

			if (handler->reset_method == AMD_RESET_METHOD_MODE2) {

				reset_context->method = AMD_RESET_METHOD_MODE2;

				return handler;

			}

		}

	}



	dev_dbg(adev->dev, "Reset handler not found!\n");



	return NULL;

}



static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev)

{

	int r, i;



	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);

	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);



	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {

		if (!(adev->ip_blocks[i].version->type ==

			      AMD_IP_BLOCK_TYPE_GFX ||

		      adev->ip_blocks[i].version->type ==

			      AMD_IP_BLOCK_TYPE_SDMA))

			continue;



		r = adev->ip_blocks[i].version->funcs->suspend(adev);



		if (r) {

			dev_err(adev->dev,

				"suspend of IP block <%s> failed %d\n",

				adev->ip_blocks[i].version->funcs->name, r);

			return r;

		}



		adev->ip_blocks[i].status.hw = false;

	}



	return r;

}



static int

aldebaran_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,

				  struct amdgpu_reset_context *reset_context)

{

	int r = 0;

	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;



	dev_dbg(adev->dev, "Aldebaran prepare hw context\n");

	/* Don't suspend on bare metal if we are not going to HW reset the ASIC */

	if (!amdgpu_sriov_vf(adev))

		r = aldebaran_mode2_suspend_ip(adev);



	return r;

}



static void aldebaran_async_reset(struct work_struct *work)

{

	struct amdgpu_reset_handler *handler;

	struct amdgpu_reset_control *reset_ctl =

		container_of(work, struct amdgpu_reset_control, reset_work);

	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;



	list_for_each_entry(handler, &reset_ctl->reset_handlers,

			     handler_list) {

		if (handler->reset_method == reset_ctl->active_reset) {

			dev_dbg(adev->dev, "Resetting device\n");

			handler->do_reset(adev);

			break;

		}

	}

}



static int aldebaran_mode2_reset(struct amdgpu_device *adev)

{

	/* disable BM */

	pci_clear_master(adev->pdev);

	adev->asic_reset_res = amdgpu_dpm_mode2_reset(adev);

	return adev->asic_reset_res;

}



static int

aldebaran_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,

			      struct amdgpu_reset_context *reset_context)

{

	struct amdgpu_device *tmp_adev = NULL;

	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;

	int r = 0;



	dev_dbg(adev->dev, "aldebaran perform hw reset\n");

	if (reset_context->hive == NULL) {

		/* Wrong context, return error */

		return -EINVAL;

	}



	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

		mutex_lock(&tmp_adev->reset_cntl->reset_lock);

		tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_MODE2;

	}

	/*

	 * Mode2 reset doesn't need any sync between nodes in XGMI hive, instead launch

	 * them together so that they can be completed asynchronously on multiple nodes

	 */

	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

		/* For XGMI run all resets in parallel to speed up the process */

		if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {

			if (!queue_work(system_unbound_wq,

					&tmp_adev->reset_cntl->reset_work))

				r = -EALREADY;

		} else

			r = aldebaran_mode2_reset(tmp_adev);

		if (r) {

			dev_err(tmp_adev->dev,

				"ASIC reset failed with error, %d for drm dev, %s",

				r, adev_to_drm(tmp_adev)->unique);

			break;

		}

	}



	/* For XGMI wait for all resets to complete before proceed */

	if (!r) {

		list_for_each_entry(tmp_adev,

				     &reset_context->hive->device_list,

				     gmc.xgmi.head) {

			if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) {

				flush_work(&tmp_adev->reset_cntl->reset_work);

				r = tmp_adev->asic_reset_res;

				if (r)

					break;

			}

		}

	}



	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

		mutex_unlock(&tmp_adev->reset_cntl->reset_lock);

		tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE;

	}



	return r;

}



static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev)

{

	struct amdgpu_firmware_info *ucode_list[AMDGPU_UCODE_ID_MAXIMUM];

	struct amdgpu_firmware_info *ucode;

	struct amdgpu_ip_block *cmn_block;

	int ucode_count = 0;

	int i, r;



	dev_dbg(adev->dev, "Reloading ucodes after reset\n");

	for (i = 0; i < adev->firmware.max_ucodes; i++) {

		ucode = &adev->firmware.ucode[i];

		if (!ucode->fw)

			continue;

		switch (ucode->ucode_id) {

		case AMDGPU_UCODE_ID_SDMA0:

		case AMDGPU_UCODE_ID_SDMA1:

		case AMDGPU_UCODE_ID_SDMA2:

		case AMDGPU_UCODE_ID_SDMA3:

		case AMDGPU_UCODE_ID_SDMA4:

		case AMDGPU_UCODE_ID_SDMA5:

		case AMDGPU_UCODE_ID_SDMA6:

		case AMDGPU_UCODE_ID_SDMA7:

		case AMDGPU_UCODE_ID_CP_MEC1:

		case AMDGPU_UCODE_ID_CP_MEC1_JT:

		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:

		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:

		case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:

		case AMDGPU_UCODE_ID_RLC_G:

			ucode_list[ucode_count++] = ucode;

			break;

		default:

			break;

		};

	}



	/* Reinit NBIF block */

	cmn_block =

		amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_COMMON);

	if (unlikely(!cmn_block)) {

		dev_err(adev->dev, "Failed to get BIF handle\n");

		return -EINVAL;

	}

	r = cmn_block->version->funcs->resume(adev);

	if (r)

		return r;



	/* Reinit GFXHUB */

	adev->gfxhub.funcs->init(adev);

	r = adev->gfxhub.funcs->gart_enable(adev);

	if (r) {

		dev_err(adev->dev, "GFXHUB gart reenable failed after reset\n");

		return r;

	}



	/* Reload GFX firmware */

	r = psp_load_fw_list(&adev->psp, ucode_list, ucode_count);

	if (r) {

		dev_err(adev->dev, "GFX ucode load failed after reset\n");

		return r;

	}



	/* Resume RLC, FW needs RLC alive to complete reset process */

	adev->gfx.rlc.funcs->resume(adev);



	/* Wait for FW reset event complete */

	r = smu_wait_for_event(adev, SMU_EVENT_RESET_COMPLETE, 0);

	if (r) {

		dev_err(adev->dev,

			"Failed to get response from firmware after reset\n");

		return r;

	}



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (!(adev->ip_blocks[i].version->type ==

			      AMD_IP_BLOCK_TYPE_GFX ||

		      adev->ip_blocks[i].version->type ==

			      AMD_IP_BLOCK_TYPE_SDMA))

			continue;

		r = adev->ip_blocks[i].version->funcs->resume(adev);

		if (r) {

			dev_err(adev->dev,

				"resume of IP block <%s> failed %d\n",

				adev->ip_blocks[i].version->funcs->name, r);

			return r;

		}



		adev->ip_blocks[i].status.hw = true;

	}



	for (i = 0; i < adev->num_ip_blocks; i++) {

		if (!(adev->ip_blocks[i].version->type ==

			      AMD_IP_BLOCK_TYPE_GFX ||

		      adev->ip_blocks[i].version->type ==

			      AMD_IP_BLOCK_TYPE_SDMA ||

		      adev->ip_blocks[i].version->type ==

			      AMD_IP_BLOCK_TYPE_COMMON))

			continue;



		if (adev->ip_blocks[i].version->funcs->late_init) {

			r = adev->ip_blocks[i].version->funcs->late_init(

				(void *)adev);

			if (r) {

				dev_err(adev->dev,

					"late_init of IP block <%s> failed %d after reset\n",

					adev->ip_blocks[i].version->funcs->name,

					r);

				return r;

			}

		}

		adev->ip_blocks[i].status.late_initialized = true;

	}



	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);

	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);



	return r;

}



static int

aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,

				  struct amdgpu_reset_context *reset_context)

{

	int r;

	struct amdgpu_device *tmp_adev = NULL;



	if (reset_context->hive == NULL) {

		/* Wrong context, return error */

		return -EINVAL;

	}



	list_for_each_entry(tmp_adev, &reset_context->hive->device_list,

			     gmc.xgmi.head) {

		dev_info(tmp_adev->dev,

			 "GPU reset succeeded, trying to resume\n");

		r = aldebaran_mode2_restore_ip(tmp_adev);

		if (r)

			goto end;



		/*

		 * Add this ASIC as tracked as reset was already

		 * complete successfully.

		 */

		amdgpu_register_gpu_instance(tmp_adev);



		/* Resume RAS */

		amdgpu_ras_resume(tmp_adev);



		/* Update PSP FW topology after reset */

		if (reset_context->hive &&

		    tmp_adev->gmc.xgmi.num_physical_nodes > 1)

			r = amdgpu_xgmi_update_topology(reset_context->hive,

							tmp_adev);



		if (!r) {

			amdgpu_irq_gpu_reset_resume_helper(tmp_adev);



			r = amdgpu_ib_ring_tests(tmp_adev);

			if (r) {

				dev_err(tmp_adev->dev,

					"ib ring test failed (%d).\n", r);

				r = -EAGAIN;

				tmp_adev->asic_reset_res = r;

				goto end;

			}

		}

	}



end:

	return r;

}



static struct amdgpu_reset_handler aldebaran_mode2_handler = {

	.reset_method		= AMD_RESET_METHOD_MODE2,

	.prepare_env		= NULL,

	.prepare_hwcontext	= aldebaran_mode2_prepare_hwcontext,

	.perform_reset		= aldebaran_mode2_perform_reset,

	.restore_hwcontext	= aldebaran_mode2_restore_hwcontext,

	.restore_env		= NULL,

	.do_reset		= aldebaran_mode2_reset,

};



int aldebaran_reset_init(struct amdgpu_device *adev)

{

	struct amdgpu_reset_control *reset_ctl;



	reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);

	if (!reset_ctl)

		return -ENOMEM;



	reset_ctl->handle = adev;

	reset_ctl->async_reset = aldebaran_async_reset;

	reset_ctl->active_reset = AMD_RESET_METHOD_NONE;

	reset_ctl->get_reset_handler = aldebaran_get_reset_handler;



	INIT_LIST_HEAD(&reset_ctl->reset_handlers);

	INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);

	/* Only mode2 is handled through reset control now */

	amdgpu_reset_add_handler(reset_ctl, &aldebaran_mode2_handler);



	adev->reset_cntl = reset_ctl;



	return 0;

}



int aldebaran_reset_fini(struct amdgpu_device *adev)

{

	kfree(adev->reset_cntl);

	adev->reset_cntl = NULL;

	return 0;

}

drivers/gpu/drm/amd/amdgpu/aldebaran.h

0 → 100644
+32 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2021 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */



#ifndef __ALDEBARAN_H__

#define __ALDEBARAN_H__



#include "amdgpu.h"



int aldebaran_reset_init(struct amdgpu_device *adev);

int aldebaran_reset_fini(struct amdgpu_device *adev);



#endif

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+21 −15
Original line number Diff line number Diff line
@@ -107,7 +107,6 @@ 
#include "amdgpu_gfxhub.h"

#include "amdgpu_df.h"

#include "amdgpu_smuio.h"

#include "amdgpu_hdp.h"



#define MAX_GPU_INSTANCE		16
@@ -271,6 +270,8 @@ struct amdgpu_bo_va_mapping; 
struct amdgpu_atif;

struct kfd_vm_fault_info;

struct amdgpu_hive_info;

struct amdgpu_reset_context;

struct amdgpu_reset_control;



enum amdgpu_cp_irq {

	AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0,
@@ -589,6 +590,7 @@ struct amdgpu_allowed_register_entry { 
};



enum amd_reset_method {

	AMD_RESET_METHOD_NONE = -1,

	AMD_RESET_METHOD_LEGACY = 0,

	AMD_RESET_METHOD_MODE0,

	AMD_RESET_METHOD_MODE1,
@@ -920,6 +922,7 @@ struct amdgpu_device { 
	struct amdgpu_irq_src		pageflip_irq;

	struct amdgpu_irq_src		hpd_irq;

	struct amdgpu_irq_src		dmub_trace_irq;

	struct amdgpu_irq_src		dmub_outbox_irq;



	/* rings */

	u64				fence_context;
@@ -1030,13 +1033,9 @@ struct amdgpu_device { 


	/* s3/s4 mask */

	bool                            in_suspend;

	bool				in_hibernate;



	/*

	 * The combination flag in_poweroff_reboot_com used to identify the poweroff

	 * and reboot opt in the s0i3 system-wide suspend.

	 */

	bool 				in_poweroff_reboot_com;

	bool				in_s3;

	bool				in_s4;

	bool				in_s0ix;



	atomic_t 			in_gpu_reset;

	enum pp_mp1_state               mp1_state;
@@ -1078,6 +1077,8 @@ struct amdgpu_device { 


	bool                            in_pci_err_recovery;

	struct pci_saved_state          *pci_state;



	struct amdgpu_reset_control     *reset_cntl;

};



static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1129,13 +1130,10 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 
bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);



int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,

				  struct amdgpu_job *job,

				  bool *need_full_reset_arg);

				 struct amdgpu_reset_context *reset_context);



int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,

			  struct list_head *device_list_handle,

			  bool *need_full_reset_arg,

			  bool skip_hw_reset);

int amdgpu_do_asic_reset(struct list_head *device_list_handle,

			 struct amdgpu_reset_context *reset_context);



int emu_soc_asic_init(struct amdgpu_device *adev);
@@ -1275,8 +1273,9 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 
					     const u32 *registers,

					     const u32 array_size);



bool amdgpu_device_supports_atpx(struct drm_device *dev);

int amdgpu_device_mode1_reset(struct amdgpu_device *adev);

bool amdgpu_device_supports_atpx(struct drm_device *dev);

bool amdgpu_device_supports_px(struct drm_device *dev);

bool amdgpu_device_supports_boco(struct drm_device *dev);

bool amdgpu_device_supports_baco(struct drm_device *dev);

bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,
@@ -1390,6 +1389,13 @@ void amdgpu_pci_resume(struct pci_dev *pdev); 
bool amdgpu_device_cache_pci_state(struct pci_dev *pdev);

bool amdgpu_device_load_pci_state(struct pci_dev *pdev);



bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev);



int amdgpu_device_set_cg_state(struct amdgpu_device *adev,

			       enum amd_clockgating_state state);

int amdgpu_device_set_pg_state(struct amdgpu_device *adev,

			       enum amd_powergating_state state);



#include "amdgpu_object.h"



static inline bool amdgpu_is_tmz(struct amdgpu_device *adev)

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+5 −3
Original line number Diff line number Diff line
@@ -246,6 +246,7 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 
	bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;

	bp.type = ttm_bo_type_kernel;

	bp.resv = NULL;

	bp.bo_ptr_size = sizeof(struct amdgpu_bo);



	if (cp_mqd_gfx9)

		bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
@@ -317,6 +318,7 @@ int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;

	struct amdgpu_bo *bo = NULL;

	struct amdgpu_bo_user *ubo;

	struct amdgpu_bo_param bp;

	int r;
@@ -327,14 +329,16 @@ int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, 
	bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;

	bp.type = ttm_bo_type_device;

	bp.resv = NULL;

	bp.bo_ptr_size = sizeof(struct amdgpu_bo);



	r = amdgpu_bo_create(adev, &bp, &bo);

	r = amdgpu_bo_create_user(adev, &bp, &ubo);

	if (r) {

		dev_err(adev->dev,

			"failed to allocate gws BO for amdkfd (%d)\n", r);

		return r;

	}



	bo = &ubo->bo;

	*mem_obj = bo;

	return 0;

}
@@ -495,8 +499,6 @@ int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd, 
		*dma_buf_kgd = (struct kgd_dev *)adev;

	if (bo_size)

		*bo_size = amdgpu_bo_size(bo);

	if (metadata_size)

		*metadata_size = bo->metadata_size;

	if (metadata_buffer)

		r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,

					   metadata_size, &metadata_flags);