Commit cd8cfbca authored by Jake Wang's avatar Jake Wang Committed by Alex Deucher
Browse files

drm/amd/display: Added new DMUB boot option for power optimization 



[Why]
During Z10, root clock gating and memory low power registers needs to
to be restored if optimization is enabled in driver.

[How]
Added new DMUB boot option for root clock gating and memory low power.

Acked-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarJake Wang <haonan.wang2@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9959125a

drivers/gpu/drm/amd/display/dmub/dmub_srv.h

+1 −0
Original line number Diff line number Diff line
@@ -238,6 +238,7 @@ struct dmub_srv_hw_params { 
	bool load_inst_const;

	bool skip_panel_power_sequence;

	bool disable_z10;

	bool power_optimization;

	bool dpia_supported;

	bool disable_dpia;

};

drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c

+1 −0
Original line number Diff line number Diff line
@@ -340,6 +340,7 @@ void dmub_dcn31_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu 
	boot_options.bits.z10_disable = params->disable_z10;

	boot_options.bits.dpia_supported = params->dpia_supported;

	boot_options.bits.enable_dpia = params->disable_dpia ? 0 : 1;

	boot_options.bits.power_optimization = params->power_optimization;



	boot_options.bits.sel_mux_phy_c_d_phy_f_g = (dmub->asic == DMUB_ASIC_DCN31B) ? 1 : 0;