Commit cd6d421e authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: Initial DC support for Beige Goby 



[Why&How]
Add Beige Goby (DCN303) resource, irq service, & dmub loader.

v2: fix nbio include (Alex)

Signed-off-by: default avatarChris Park <Chris.Park@amd.com>
Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8198ace7

drivers/gpu/drm/amd/display/dc/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ DC_LIBS += dcn21 
DC_LIBS += dcn30

DC_LIBS += dcn301

DC_LIBS += dcn302

DC_LIBS += dcn303

endif



DC_LIBS += dce120

drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c

+1 −0
Original line number Diff line number Diff line
@@ -73,6 +73,7 @@ bool dal_bios_parser_init_cmd_tbl_helper2( 
	case DCN_VERSION_3_0:

	case DCN_VERSION_3_01:

	case DCN_VERSION_3_02:

	case DCN_VERSION_3_03:

		*h = dal_cmd_tbl_helper_dce112_get_table2();

		return true;

#endif

drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c

+7 −0
Original line number Diff line number Diff line
@@ -241,6 +241,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p 
			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

			return &clk_mgr->base;

		}

		if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev)) {

			dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

			return &clk_mgr->base;

		}

		dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);

		return &clk_mgr->base;

	}
@@ -278,6 +282,9 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) 
		if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {

			dcn3_clk_mgr_destroy(clk_mgr);

		}

		if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) {

			dcn3_clk_mgr_destroy(clk_mgr);

		}

		break;



	case FAMILY_VGH:

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+6 −0
Original line number Diff line number Diff line
@@ -57,6 +57,7 @@ 
#include "dcn30/dcn30_resource.h"

#include "dcn301/dcn301_resource.h"

#include "dcn302/dcn302_resource.h"

#include "dcn303/dcn303_resource.h"

#endif



#define DC_LOGGER_INIT(logger)
@@ -130,6 +131,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) 
			dc_version = DCN_VERSION_3_0;

		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))

			dc_version = DCN_VERSION_3_02;

		if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))

			dc_version = DCN_VERSION_3_03;

		break;



	case FAMILY_VGH:
@@ -216,6 +219,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, 
	case DCN_VERSION_3_02:

		res_pool = dcn302_create_resource_pool(init_data, dc);

		break;

	case DCN_VERSION_3_03:

		res_pool = dcn303_create_resource_pool(init_data, dc);

		break;

#endif

	default:

		break;

drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h

+9 −0
Original line number Diff line number Diff line
@@ -142,6 +142,15 @@ 
		SRII(PIXEL_RATE_CNTL, OTG, 3),\

		SRII(PIXEL_RATE_CNTL, OTG, 4)



#define CS_COMMON_REG_LIST_DCN3_03(index, pllid) \

		SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\

		SRII(PHASE, DP_DTO, 0),\

		SRII(PHASE, DP_DTO, 1),\

		SRII(MODULO, DP_DTO, 0),\

		SRII(MODULO, DP_DTO, 1),\

		SRII(PIXEL_RATE_CNTL, OTG, 0),\

		SRII(PIXEL_RATE_CNTL, OTG, 1)



#endif

#define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\

	CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\